Inventor
CHIN KENNETH T
US21 patents
⚠️ This page may combine multiple inventors who share the name “CHIN KENNETH T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
COMPAQ COMPUTER CORP
11 patentsUS6286083B1Sep 4, 2001
Computer system with adaptive memory arbitration scheme
COMPAQ COMPUTER CORP213 citations98
US6275885B1Aug 14, 2001
System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache
COMPAQ COMPUTER CORP71 citations96
US6247102B1Jun 12, 2001
Computer system employing memory controller and bridge interface permitting concurrent operation
COMPAQ COMPUTER CORP68 citations96
US6202101B1Mar 13, 2001
System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
COMPAQ COMPUTER CORP58 citations96
US6160562ADec 12, 2000
System and method for aligning an initial cache line of data read from local memory by an input/output device
COMPAQ COMPUTER CORP73 citations96
US6272651B1Aug 7, 2001
System and method for improving processor read latency in a system employing error checking and correction
COMPAQ COMPUTER CORP61 citations93
US6279065B1Aug 21, 2001
Computer system with improved memory access
COMPAQ COMPUTER CORP43 citations92
US6209052B1Mar 27, 2001
System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter
COMPAQ COMPUTER CORP23 citations92
US6249847B1Jun 19, 2001
Computer system with synchronous memory arbiter that permits asynchronous memory requests
COMPAQ COMPUTER CORP17 citations84
US6199118B1Mar 6, 2001
System and method for aligning an initial cache line of data read from an input/output device by a central processing unit
COMPAQ COMPUTER CORP15 citations84
US6216190B1Apr 10, 2001
System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus
COMPAQ COMPUTER CORP12 citations74
HEWLETT PACKARD ENTPR DEV LP
4 patentsUS10372400B2Aug 6, 2019
Video management for compute nodes
HEWLETT PACKARD ENTPR DEV LP1 citations62
US11360782B2Jun 14, 2022
Processors to configure subsystems while other processors are held in reset
HEWLETT PACKARD ENTPR DEV LP0 citations60
US11138140B2Oct 5, 2021
Configuring first subsystem with a master processor and a second subsystem with a slave processor
HEWLETT PACKARD ENTPR DEV LP0 citations60
US10404244B2Sep 3, 2019
Adjustments of output clocks
HEWLETT PACKARD ENTPR DEV LP0 citations48
HEWLETT PACKARD DEVELOPMENT CO
3 patentsUS6829665B2Dec 7, 2004
Next snoop predictor in a host controller
HEWLETT PACKARD DEVELOPMENT CO17 citations84
US6961800B2Nov 1, 2005
Method for improving processor performance
HEWLETT PACKARD DEVELOPMENT CO2 citations60
US7876759B2Jan 25, 2011
Quality of service with control flow packet filtering
HEWLETT PACKARD DEVELOPMENT CO0 citations50
COMPAQ INFORMATION TECHNOLOGIE
2 patentsUS6505260B2Jan 7, 2003
Computer system with adaptive memory arbitration scheme
COMPAQ INFORMATION TECHNOLOGIE34 citations92
US6356972B1Mar 12, 2002
System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
COMPAQ INFORMATION TECHNOLOGIE34 citations92