Inventor
JOHNSON JEROME J
US30 patents
⚠️ This page may combine multiple inventors who share the name “JOHNSON JEROME J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEWLETT PACKARD DEVELOPMENT CO
15 patentsUS7194577B2Mar 20, 2007
Memory latency and bandwidth optimizations
HEWLETT PACKARD DEVELOPMENT CO128 citations99
US7010652B2Mar 7, 2006
Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency
HEWLETT PACKARD DEVELOPMENT CO136 citations99
US6938133B2Aug 30, 2005
Memory latency and bandwidth optimizations
HEWLETT PACKARD DEVELOPMENT CO144 citations99
US6785785B2Aug 31, 2004
Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency
HEWLETT PACKARD DEVELOPMENT CO140 citations99
US6684292B2Jan 27, 2004
Memory module resync
HEWLETT PACKARD DEVELOPMENT CO148 citations99
US6832340B2Dec 14, 2004
Real-time hardware memory scrubbing
HEWLETT PACKARD DEVELOPMENT CO90 citations98
US6854070B2Feb 8, 2005
Hot-upgrade/hot-add memory
HEWLETT PACKARD DEVELOPMENT CO75 citations97
US6766469B2Jul 20, 2004
Hot-replace of memory
HEWLETT PACKARD DEVELOPMENT CO139 citations97
US6785835B2Aug 31, 2004
Raid memory
HEWLETT PACKARD DEVELOPMENT CO47 citations96
US6640282B2Oct 28, 2003
Hot replace power control sequence logic
HEWLETT PACKARD DEVELOPMENT CO25 citations92
US7320086B2Jan 15, 2008
Error indication in a raid memory system
HEWLETT PACKARD DEVELOPMENT CO41 citations91
US7028213B2Apr 11, 2006
Error indication in a raid memory system
HEWLETT PACKARD DEVELOPMENT CO36 citations91
US6981095B1Dec 27, 2005
Hot replace power control sequence logic
HEWLETT PACKARD DEVELOPMENT CO12 citations84
US6892271B2May 10, 2005
Memory module resync
HEWLETT PACKARD DEVELOPMENT CO13 citations84
US6832286B2Dec 14, 2004
Memory auto-precharge
HEWLETT PACKARD DEVELOPMENT CO17 citations84
COMPAQ COMPUTER CORP
10 patentsUS6286083B1Sep 4, 2001
Computer system with adaptive memory arbitration scheme
COMPAQ COMPUTER CORP213 citations98
US6247102B1Jun 12, 2001
Computer system employing memory controller and bridge interface permitting concurrent operation
COMPAQ COMPUTER CORP68 citations96
US6202101B1Mar 13, 2001
System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
COMPAQ COMPUTER CORP58 citations96
US6160562ADec 12, 2000
System and method for aligning an initial cache line of data read from local memory by an input/output device
COMPAQ COMPUTER CORP73 citations96
US5949436ASep 7, 1999
Accelerated graphics port multiple entry gart cache allocation system and method
COMPAQ COMPUTER CORP67 citations96
US6272651B1Aug 7, 2001
System and method for improving processor read latency in a system employing error checking and correction
COMPAQ COMPUTER CORP61 citations93
US6279065B1Aug 21, 2001
Computer system with improved memory access
COMPAQ COMPUTER CORP43 citations92
US6209052B1Mar 27, 2001
System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter
COMPAQ COMPUTER CORP23 citations92
US6199118B1Mar 6, 2001
System and method for aligning an initial cache line of data read from an input/output device by a central processing unit
COMPAQ COMPUTER CORP15 citations84
US6216190B1Apr 10, 2001
System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus
COMPAQ COMPUTER CORP12 citations74
CADENCE DESIGN SYSTEMS INC
3 patentsUS10275306B1Apr 30, 2019
System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations
CADENCE DESIGN SYSTEMS INC14 citations83
US10719058B1Jul 21, 2020
System and method for memory control having selectively distributed power-on processing
CADENCE DESIGN SYSTEMS INC11 citations80
US10956342B1Mar 23, 2021
Variable channel multi-controller memory system
CADENCE DESIGN SYSTEMS INC5 citations70
COMPAQ INFORMATION TECHNOLOGIE
2 patentsUS6505260B2Jan 7, 2003
Computer system with adaptive memory arbitration scheme
COMPAQ INFORMATION TECHNOLOGIE34 citations92
US6356972B1Mar 12, 2002
System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
COMPAQ INFORMATION TECHNOLOGIE34 citations92