Inventor

JONES PHILLIP M

US37 patents

⚠️ This page may combine multiple inventors who share the name “JONES PHILLIP M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JONES PHILLIP M

COMPAQ COMPUTER CORP

Computer system with adaptive memory arbitration scheme

Memory controller using queue look-ahead to reduce memory latency

Computer system employing memory controller and bridge interface permitting concurrent operation

System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom

System and method for aligning an initial cache line of data read from local memory by an input/output device

Accelerated graphics port programmable memory access arbiter

Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device

Accelerated graphics port read transaction merging

Accelerated graphics port multiple entry gart cache allocation system and method

Accelerated graphics port memory mapped status and control registers

Accelerated Graphics Port two level Gart cache having distributed first level caches

System and method for improving processor read latency in a system employing error checking and correction

Computer system with memory controller that hides the next cycle during the current cycle

Computer system with improved memory access

Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system

System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter

System and method for dynamically allocating accelerated graphics port memory space

Generating an error signal when accessing an invalid memory page

Valid flag for disabling allocation of accelerated graphics port memory space

Computer system with synchronous memory arbiter that permits asynchronous memory requests

System and method for aligning an initial cache line of data read from an input/output device by a central processing unit

System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus

HEWLETT PACKARD DEVELOPMENT CO

Dynamic cache partitioning

Arbitration technique based on processor task priority

Dynamic cache partitioning

Coherency control module for maintaining cache coherency in a multi-processor-bus system

Next snoop predictor in a host controller

Method for improving processor performance

Technique for improving processor performance

COMPAQ INFORMATION TECHNOLOGIE

System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops

Computer system with adaptive memory arbitration scheme

Apparatus for identifying memory requests originating on remote I/O devices as noncacheable

System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom

QUALCOMM INC

Speculative addressing using a virtual address-to-physical address page crossing buffer

Multi-mode instruction memory unit

VENKUMAHANTI SURESH K

Bimodal branch predictor encoded in a branch instruction

WALKER WILLIAM J

Method and system for migrating memory segments