Inventor

LESTER ROBERT A

US43 patents

⚠️ This page may combine multiple inventors who share the name “LESTER ROBERT A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LESTER ROBERT A

COMPAQ COMPUTER CORP

Computer system with adaptive memory arbitration scheme

System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache

Computer system employing memory controller and bridge interface permitting concurrent operation

System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom

System and method for aligning an initial cache line of data read from local memory by an input/output device

Interfacing direct memory access devices to a non-ISA bus

First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus

Computer system with improved memory access

Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system

System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter

Interfacing direct memory access devices to a non-ISA bus

Direct memory access controller having programmable timing

Computer system with synchronous memory arbiter that permits asynchronous memory requests

System and method for aligning an initial cache line of data read from an input/output device by a central processing unit

System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus

HEWLETT PACKARD DEVELOPMENT CO

Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency

Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency

Real-time hardware memory scrubbing

Hot-upgrade/hot-add memory

Hot-replace of memory

Raid memory

Rebuild bus utilization

Hot replace power control sequence logic

Error indication in a raid memory system

Error indication in a raid memory system

Hot replace power control sequence logic

Handling memory errors in response to adding new memory to a system

Method for improving processor performance

Technique for improving processor performance

WESTERN ATLAS INT INC

Synchronized digital stacking method and application to induction logging tools

Acoustic isolator for a borehole logging tool

System for acoustically determining the quality of the cement bond in a cased borehole

Method and system for determining the azimuth position and distance of a reflecting subsurface formation

Borehole logging tool

Acoustic dipole well logging instrument

Method and apparatus for balancing the electrical output of the receiver coils of an induction logging tool by use of a slidable magnetic rod for eliminating direct coupling

COMPAQ INFORMATION TECHNOLOGIE

Computer system with adaptive memory arbitration scheme

System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom

SCHLUMBERGER TECHNOLOGY CORP

Method and apparatus for cement bond logging

Method and apparatus for cement bond tool

HEWLETT PACKARD COMPANY L P

Memory data verify operation

VENKUMAHANTI SURESH K

Interleaved architecture tracing and microarchitecture tracing

QUALCOMM INC

Dual-voltage domain memory buffers, and related systems and methods