Inventor

TRAN LUAN C

US164 patents

⚠️ This page may combine multiple inventors who share the name “TRAN LUAN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAN LUAN C

MICRON TECHNOLOGY INC

Band-engineered multi-gated non-volatile memory device with enhanced attributes

Method of forming DRAM access transistors

Trench buried bit line memory devices

6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array

Dynamic flash memory cells with ultrathin tunnel oxides

Dynamic flash memory cells with ultra thin tunnel oxides

Reduced power DRAM device and method

Method of forming isolated features using pitch multiplication

DRAM access transistor

Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

Trench buried bit line memory devices and methods thereof

Semiconductor constructions, and methods of forming semiconductor constructions

Semiconductor constructions

Semiconductor constructions, and methods of forming semiconductor constructions

Methods of forming semiconductor structures

Low voltage high performance semiconductor devices and methods

Integrated circuit fabrication

Double LDD devices for improved DRAM refresh

Double LDD devices for improved dram refresh

Integrated circuit fabrication

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Pitch multiplied mask patterns for isolated features

Method of forming pitch multipled contacts

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Band-engineered multi-gated non-volatile memory device with enhanced attributes

DRAM access transistor

Methods of forming DRAM arrays

DRAM arrays

Methods of forming memory arrays; and methods of forming contacts to bitlines

Method to construct a self aligned recess gate for DRAM access devices

Methods of forming electrical connections for semiconductor constructions

Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

Methods of forming semiconductor structures

Method of forming memory cells in an array

Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays

Semiconductor processing methods of forming integrated circuitry

Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory dram circuitry

Reference charge generator, a method for providing a reference charge from a reference charge generator, a method of operating a reference charge generator and a dram memory circuit formed using memory cells having an area of 6f2

Semiconductor processing methods of forming contact openings

Memory device having pipelined access and method for pipelining data access

Methods of forming openings, and methods of forming container capacitors

Trench buried bit line memory devices and methods thereof

Capacitor structures, and DRAM arrays

Methods of forming openings, and methods of forming container capacitors

TRAN LUAN C

Integrated circuit fabrication

Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures

Integrated circuit fabrication

Integrated circuit fabrication

HUNG CHIH-WEI

Non-volatile field programmable gate array

BHATTACHARYYA ARUP

Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material