Inventor

MCMINN BRIAN D

US37 patents

⚠️ This page may combine multiple inventors who share the name “MCMINN BRIAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCMINN BRIAN D

ADVANCED MICRO DEVICES INC

Cache including a prefetch way for storing cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line

Storage circuit with data retention during power down

Data transaction typing for improved caching and prefetching characteristics

Normalizing pipelined floating point processing unit

Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line

Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

Context-dependent memory-mapped registers for transparent expansion of a register file

Self-regulating clock generator

Pipelined floating point processing unit

Memory including logic for operating upon graphics primitives

Circuit configuration employing a compare unit for testing variably controlled delay units

Configuration and method for testing a delay chain within a microprocessor clock generator

High speed intelligent distributed control memory system

System and method for scheduling operations using speculative data operands

Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots

System and method for handling exceptional instructions in a trace cache based processor

Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions

Circular buffer using grouping for find first function

Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer

Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same

Method to transfer data in a system with multiple clock domains using clock skipping techniques

Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

Apparatus and method for efficient loop control in a superscalar microprocessor

Normalizing pipelined floating point processing unit

Reorder buffer circuit accommodating special instructions operating on odd-width results

Circular buffer using age vectors

Mapper circuit with backup capability

Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios

Method for transfering data between two different clock domains by calculating which pulses of the faster clock domain should be skipped substantially simultaneously with the transfer

Constraint management and validation for template-based circuit design

Segmented read line circuit particularly useful for multi-port storage arrays

Integrated circuit with multiple microcode ROMs

Information storage device with batch select capability

Simulation by emulating level sensitive latches with edge trigger latches

Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right

GLOBALFOUNDRIES INC

Data processor having a cache with efficient storage of predecode information, cache, and method