P

Inventor

WU KUO-CHIEN

TW20 patents
⚠️ This page may combine multiple inventors who share the name “WU KUO-CHIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NANYA TECHNOLOGY CORP

19 patents
US6797611B1Sep 28, 2004

Method of fabricating contact holes on a semiconductor chip

NANYA TECHNOLOGY CORP24 citations92
US7115491B2Oct 3, 2006

Method for forming self-aligned contact in semiconductor device

NANYA TECHNOLOGY CORP15 citations84
US6979613B1Dec 27, 2005

Method for fabricating a trench capacitor of DRAM

NANYA TECHNOLOGY CORP12 citations83
US6960503B2Nov 1, 2005

Method for fabricating a trench capacitor

NANYA TECHNOLOGY CORP14 citations83
US6960530B2Nov 1, 2005

Method of reducing the aspect ratio of a trench

NANYA TECHNOLOGY CORP8 citations73
US6991978B2Jan 31, 2006

World line structure with single-sided partially recessed gate structure

NANYA TECHNOLOGY CORP3 citations62
US6953725B2Oct 11, 2005

Method for fabricating memory device having a deep trench capacitor

NANYA TECHNOLOGY CORP4 citations62
US6933229B2Aug 23, 2005

Method of manufacturing semiconductor device featuring formation of conductive plugs

NANYA TECHNOLOGY CORP2 citations62
US6797564B1Sep 28, 2004

Method of forming bit lines and bit line contacts in a memory device

NANYA TECHNOLOGY CORP3 citations62
US6790771B2Sep 14, 2004

Bitline structure for DRAM and method of forming the same

NANYA TECHNOLOGY CORP4 citations62
US6743717B1Jun 1, 2004

Method for forming silicide at source and drain

NANYA TECHNOLOGY CORP4 citations62
US7358576B2Apr 15, 2008

Word line structure with single-sided partially recessed gate structure

NANYA TECHNOLOGY CORP0 citations51
US7075138B2Jul 11, 2006

Bitline structure for DRAM and method of forming the same

NANYA TECHNOLOGY CORP0 citations51
US7030011B2Apr 18, 2006

Method for avoiding short-circuit of conductive wires

NANYA TECHNOLOGY CORP0 citations51
US6943099B2Sep 13, 2005

Method for manufacturing gate structure with sides of its metal layer partially removed

NANYA TECHNOLOGY CORP0 citations51
US6930043B2Aug 16, 2005

Method for forming DRAM cell bit line and bit line contact structure

NANYA TECHNOLOGY CORP0 citations51
US6972248B2Dec 6, 2005

Method of fabricating semiconductor device

NANYA TECHNOLOGY CORP1 citations50
US7052949B2May 30, 2006

Method for forming bit line

NANYA TECHNOLOGY CORP0 citations42
US7033885B2Apr 25, 2006

Deep trench structure manufacturing process

NANYA TECHNOLOGY CORP0 citations41

HOLTEK MICROELECTRONICS INC

1 patent