Inventor
RAJSUMAN ROCHIT
US29 patents
⚠️ This page may combine multiple inventors who share the name “RAJSUMAN ROCHIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANTEST CORP
23 patentsUS6678645B1Jan 13, 2004
Method and apparatus for SoC design validation
ADVANTEST CORP276 citations99
US6249893B1Jun 19, 2001
Method and structure for testing embedded cores based system-on-a-chip
ADVANTEST CORP199 citations99
US6651204B1Nov 18, 2003
Modular architecture for memory testing on event based test system
ADVANTEST CORP64 citations96
US6629282B1Sep 30, 2003
Module based flexible semiconductor test system
ADVANTEST CORP59 citations96
US6532561B1Mar 11, 2003
Event based semiconductor test system
ADVANTEST CORP62 citations96
US6408412B1Jun 18, 2002
Method and structure for testing embedded analog/mixed-signal cores in system-on-a-chip
ADVANTEST CORP56 citations96
US7089517B2Aug 8, 2006
Method for design validation of complex IC
ADVANTEST CORP23 citations92
US6948105B2Sep 20, 2005
Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same
ADVANTEST CORP24 citations92
US6567941B1May 20, 2003
Event based test system storing pin calibration data in non-volatile memory
ADVANTEST CORP43 citations92
US6404218B1Jun 11, 2002
Multiple end of test signal for event based test system
ADVANTEST CORP24 citations92
US6377065B1Apr 23, 2002
Glitch detection for semiconductor test system
ADVANTEST CORP50 citations92
US6249892B1Jun 19, 2001
Circuit structure for testing microprocessors and test method thereof
ADVANTEST CORP37 citations92
US6249889B1Jun 19, 2001
Method and structure for testing embedded memories
ADVANTEST CORP44 citations92
US6747447B2Jun 8, 2004
Locking apparatus and loadboard assembly
ADVANTEST CORP30 citations89
US6804620B1Oct 12, 2004
Calibration method for system performance validation of automatic test equipment
ADVANTEST CORP31 citations88
US7178115B2Feb 13, 2007
Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing
ADVANTEST CORP15 citations84
US6578169B1Jun 10, 2003
Data failure memory compaction for semiconductor test system
ADVANTEST CORP19 citations84
US7089135B2Aug 8, 2006
Event based IC test system
ADVANTEST CORP15 citations82
US6944808B2Sep 13, 2005
Method of evaluating core based system-on-a-chip
ADVANTEST CORP5 citations63
US6915469B2Jul 5, 2005
High speed vector access method from pattern memory for test systems
ADVANTEST CORP2 citations63
US6594609B1Jul 15, 2003
Scan vector support for event based test system
ADVANTEST CORP6 citations63
US7194668B2Mar 20, 2007
Event based test method for debugging timing related failures in integrated circuits
ADVANTEST CORP2 citations56
US6791316B2Sep 14, 2004
High speed semiconductor test system using radially arranged pin cards
ADVANTEST CORP1 citations52
LSI LOGIC CORP
5 patentsUS5670890ASep 23, 1997
Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
LSI LOGIC CORP55 citations93
US6108805AAug 22, 2000
Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits
LSI LOGIC CORP43 citations92
US5963566AOct 5, 1999
Application specific integrated circuit chip and method of testing same
LSI LOGIC CORP28 citations92
US5867036AFeb 2, 1999
Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits
LSI LOGIC CORP25 citations92
US5644251AJul 1, 1997
Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
LSI LOGIC CORP35 citations89