Inventor

IEONG MEIKEI

US88 patents

⚠️ This page may combine multiple inventors who share the name “IEONG MEIKEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IEONG MEIKEI

IBM

Three dimensional integrated circuit and method of design

Metal gated ultra short MOSFET devices

Method for metal gated ultra short MOSFET devices

Ultra thin body fully-depleted SOI MOSFETs

Metal gated ultra short MOSFET devices

High-performance CMOS devices on hybrid crystal oriented substrates

Three dimensional integrated circuit

Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS

CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding

Ultra-thin body super-steep retrograde well (SSRW) FET devices

High performance CMOS device structure with mid-gap metal gate

Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes

Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations

Variable threshold voltage double gated transistors and method of fabrication

Strained finFET CMOS device structures

Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs

Double gated transistor and method of fabrication

Integration of strained Ge into advanced CMOS technology

Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations

Strained silicon CMOS on hybrid crystal orientations

Hybrid planar and finFET CMOS devices

Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

High performance CMOS device structure with mid-gap metal gate

Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices

Ultra-thin Si MOSFET device structure and method of manufacture

Method to form Si-containing SOI and underlying substrate with different orientations

Ultra thin body fully-depleted SOI MOSFETs

CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding

Double gated transistor and method of fabrication

Self-aligned planar double-gate transistor structure

Self-aligned planar double-gate process by self-aligned oxidation

Ultra-thin Si channel CMOS with improved series resistance

Double gated vertical transistor with different first and second gate materials

Self-aligned isolation double-gate FET

Ultra thin channel MOSFET

Self-aligned planar double-gate process by amorphization

Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS

Buried stress isolation for high-performance CMOS technology

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Highly manufacturable SRAM cells in substrates with hybrid crystal orientation

Super hybrid SOI CMOS devices

Strained MOS devices using source/drain epitaxy

Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETS

Integration of strained Ge into advanced CMOS technology

Buried stress isolation for high-performance CMOS technology

Self-aligned isolation double-gate FET

INTERNAT BUSINSESS MACHINES CO

MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

CHAN VICTOR

Dual trench isolation for CMOS with hybrid orientations

CHANG LELAND

Contact scheme for FINFET structures with multiple FINs