Inventor

ERB DARRELL M

US41 patents

⚠️ This page may combine multiple inventors who share the name “ERB DARRELL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ERB DARRELL M

ADVANCED MICRO DEVICES INC

Copper interconnects with metal capping layer and selective copper alloys

High planarity high-density in-laid metallization patterns by damascene-CMP processing

Process for alloying damascene-type Cu interconnect lines

Shallow groove capacitor fabrication method

Bias plasma deposition for selective low dielectric insulation

Stabilizing fluorine etching of low-k materials

Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration

Selective deposition process for allowing damascene-type Cu interconnect lines

Silicon carbide barc in dual damascene processing

Selective deposition process for passivating top interface of damascene-type Cu interconnect lines

Process for passivating top interface of damascene-type Cu interconnect lines

Method and apparatus for improved planarity metallization by electroplating and CMP

Method for making improved contact for integrated circuit structure

Method of manufacturing high capacity semiconductor capacitance devices

Method of forming a selective barrier layer using a sacrificial layer

Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration

Copper interconnect with improved barrier layer

Chemically removable Cu CMP slurry abrasive

Chemically removable Cu CMP slurry abrasive

Bias plasma deposition for selective low dielectric insulation

Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines

Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device

High density dram trench capacitor isolation employing double epitaxial layers

Composite tantalum nitride/tantalum copper capping layer

Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer

Anneal hillock suppression method in integrated circuit interconnects

Diffusion barrier and method for its production

Use of an alloying element to form a stable oxide layer on the surface of metal features

Selective electroplating with direct contact chemical polishing

Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer

Optimizing doping control in short channel MOS

High capacity semiconductor capacitance device structure

Method of manufacturing a buried contact in semiconductor device

Anti-reflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies

Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies

Optimizing doping control in short channel MOS

Self-aligned conductive plugs in a semiconductor device

Low temperature dielectric deposition to improve copper electromigration performance

ERB DARRELL M

Memory device in which one type carrier stored during write controls the flow of the other type carrier during read

Stratified charge ram having an opposite dopant polarity MOSFET switching circuit

HUGHES AIRCRAFT CO

Charge coupled device with input for direct injection of signal