Inventor

STEPHAN ROLF

DE38 patents

⚠️ This page may combine multiple inventors who share the name “STEPHAN ROLF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEPHAN ROLF

ADVANCED MICRO DEVICES INC

Semiconductor device having a retrograde dopant profile in a channel region

Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same

Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same

Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device

Field effect transistor with an improved gate contact and method of fabricating the same

Method of forming low resistance metal silicide region on a gate electrode of a transistor

Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same

Method of forming a transistor having a low-resistance gate electrode

Method and system for increasing product yield by controlling lithography on the basis of electrical speed data

Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device

Semiconductor device having improved doping profiles and a method of improving the doping profiles of a semiconductor device

Sidewall spacer based fet alignment technology

Field effect transistor with reduced gate delay and method of fabricating the same

Semiconductor device having increased metal silicide portions and method of forming the semiconductor

Field effect transistors and methods for fabricating the same

Method of forming different silicide portions on different silicon-containing regions in a semiconductor device

Semiconductor device having T-shaped gate structure comprising in situ sidewall spacers and method of forming the semiconductor device

Semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device

Method of removing features using an improved removal process in the fabrication of a semiconductor device

Semiconductor device having improved doping profiles and method of improving the doping profiles of a semiconductor device

Method of assessing lateral dopant and/or charge carrier profiles

Method of forming a semiconductor device having T-shaped gate structure

Method for fully self-aligned FET technology

Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques

Semiconductor device having improved halo structures and a method of forming the halo structures of a semiconductor device

Field effect transistor having a stressed dielectric layer based on an enhanced device topography

Field effect transistor and method of forming a field effect transistor

GLOBALFOUNDRIES INC

Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure

Method of forming a semiconductor structure

TRENTZSCH MARTIN

Reducing the creation of charge traps at gate dielectrics in MOS transistors by performing a hydrogen treatment

In situ monitoring of metal contamination during microstructure processing

STEPHAN ROLF

Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials

BAARS PETER

Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill

HEMPEL KLAUS

High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology

BEYER SVEN

Semiconductor device comprising a metal gate stack of reduced height and method of forming the same

FEUDEL THOMAS

Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process