Inventor

HETHERINGTON RICKY C

US58 patents

⚠️ This page may combine multiple inventors who share the name “HETHERINGTON RICKY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HETHERINGTON RICKY C

SUN MICROSYSTEMS INC

Precise error handling in a fine grain multithreaded multicore processor

Apparatus and method for distributed non-blocking multi-level cache

Apparatus for dynamically reconfiguring a processor

Speculative cache line write backs to avoid hotspots

Method for dynamically reconfiguring a processor

Multiple-core processor with flexible mapping of processor cores to cache banks

Apparatus and method for handling multiple mergeable misses in a non-blocking cache

Multiple-core processor with flexible cache directory scheme

Method and apparatus for moderating current demand in an integrated circuit processor

Cache tag caching

Cache with reduced tag information storage

Inclusion vector architecture for a level two cache

Apparatus for executing coded dependent instructions having variable latencies

Method for thermal overload detection and prevention for an intergrated circuit processor

Processor and method for device-specific memory address translation

Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags

Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine

ECC encoding for uncorrectable errors

Apparatus and method for fine-grained multithreading in a multipipelined processor core

Method and apparatus for power throttling in a multi-thread processor

Method for inhibiting thrashing in a multi-level non-blocking cache system

Multi-level non-blocking cache system with inhibiting thrashing

In-line bank conflict detection and resolution in a multi-ported non-blocking cache

Method for non-intrusive cache fills and handling of load misses

Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies

Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions

System for thermal overload detection and prevention for an integrated circuit processor

Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache

System interface unit

Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols

Method for operating a non-blocking hierarchical cache throttle

Non-blocking hierarchical cache throttle

Reducing cache misses by snarfing writebacks in non-inclusive memory systems

DIGITAL EQUIPMENT CORP

Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

Delay compensated signal propagation

System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

Method and apparatus for ordering and queueing multiple memory requests

Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system

Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system

Write back buffer with error correcting capabilities

Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

Integrated circuit chip having primary and secondary random access memories for a hierarchical cache

Method and apparatus for detecting and correcting errors in a pipelined computer system

Distributed data bus sequencing for a system bus with separate address and data bus protocols

Distributed data bus sequencing for a system bus with separate address and data bus protocols

System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation

System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register

ORACLE AMERICA INC

Multiple-core processor with support for multiple virtual processors

KAPIL SANJIV

Cache coherent support for flash in a memory hierarchy

COMPAQ COMPUTER CORP

Apparatus for determining memory bank availability in a computer system