Inventor

URAKAWA YUKIHIRO

JP40 patents

⚠️ This page may combine multiple inventors who share the name “URAKAWA YUKIHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

URAKAWA YUKIHIRO

TOSHIBA KK

Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit

Stacked MOSFET protection circuit

Memory chip and semiconductor device using the memory chip and manufacturing method of those

I/O interface circuit, semiconductor chip and semiconductor system

I/O interface circuit, semiconductor chip and semiconductor system

Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit

Semiconductor integrated circuit and method for testing a semiconductor integrated circuit

LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit

Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device

Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device

Semiconductor device having bipolar transistor and MOS transistor

Band-gap type voltage generating circuit for an ECL circuit

Logic level converting circuit

Semiconductor integrated circuit wiring design method and semiconductor integrated circuit

Self-repairing semiconductor device having a testing unit for testing under various operating conditions

Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device

Semiconductor integrated circuit

Synchronous random access memory

Semiconductor memory device having refresh circuits

BiCMOS logic circuit with bipolar transistor and MOS transistor formed on the same semiconductor substrate

Sense amplifier circuit for reducing transmission delay in data line

Semiconductor logic circuit with a bipolar current mirror arrangement

Semiconductor memory device and trimming method thereof

Memory chip and semiconductor device using the memory chip and manufacturing method of those

Programmable ROM

Upper-layer metal power standard cell

Thermal management system

Chip on chip device including basic chips capable of functioning independently from each other, and a system in package device including the chip on chip device

Semiconductor device

Semiconductor integrated circuit device having flip-flops that can be reset easily

Semiconductor device having bipolar transistor and MOS transistor

Semiconductor integrated circuit device

Semiconductor integrated circuit wiring design method and semiconductor integrated circuit

Semiconductor integrated circuit

URAKAWA YUKIHIRO

System in package device

Stacked-chip device

Semiconductor device, semiconductor package and memory repair method

Stacked-chip device

KUSHIYAMA NATSUKI

Semiconductor integrated circuit

KAWASUMI ATSUSHI

Semiconductor integrated memory circuit and trimming method thereof