Inventor

JI BRIAN L

US40 patents

⚠️ This page may combine multiple inventors who share the name “JI BRIAN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JI BRIAN L

IBM

Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors

Hierarchical power supply noise monitoring device and system for very large scale integrated circuits

Write operations for phase-change-material memory

Non-volatile content addressable memory using phase-change-material memory elements

Content addressable memory having reduced power consumption

Back-gated fully depleted SOI transistor

Destructive-read random access memory system buffered with destructive-read memory cache

Global planarization of wafer scale package with precision die thickness control

Method and system for optimizing transmission and reception power levels in a communication system

Multi-generator, partial array Vt tracking system to improve array retention time

Write operations for phase-change-material memory

Multi-port dynamic memory structures

Segmented content addressable memory architecture for improved cycle time and reduced power consumption

Destructive-read random access memory system buffered with destructive-read memory cache

On-chip electrically alterable resistor

Precision tuning of a phase-change resistive element

Adaptive data transmitter having rewriteable non-volatile storage

Destructive-read random access memory system buffered with destructive-read memory cache

Content addressable memory array

Content addressable memory reference clock

High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion

High-speed multi-mode receiver

Methods and apparatus for inline variability measurement of integrated circuit components

Wordline decoder system and method

Content addressable memory using phase change devices

On-chip electrically alterable resistor

Apparatus and method for shielding a wafer from charged particles during plasma etching

Methods and apparatus for inline variability measurement of integrated circuit components

CHANG LELAND

Content addressable memory array programmed to perform logic operations

Low voltage signaling

Bi-directional self-aligned FET capacitor

Bi-directional self-aligned FET capacitor

DENNARD ROBERT H

Voltage conversion and integrated circuits with stacked voltage domains

Voltage conversion and integrated circuits with stacked voltage domains

Switched capacitor voltage converters

Switched capacitor voltage converters

CARPENTER GARY D

Integratable efficient switching down converter

HSU LOUIS L

Air channel interconnects for 3-D integration

CAI JIN

Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors

JI BRIAN L

Ternary content addressable memory using phase change devices