Inventor

WINSTEAD BRIAN A

US49 patents

⚠️ This page may combine multiple inventors who share the name “WINSTEAD BRIAN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WINSTEAD BRIAN A

FREESCALE SEMICONDUCTOR INC

Dual surface SOI by lateral epitaxial overgrowth

Method and apparatus for performance enhancement in an asymmetrical semiconductor device

Stressed semiconductor device and method for making

Split-gate thin film storage NVM cell with reduced load-up/trap-up effects

Source/drain stressors formed using in-situ epitaxial growth

Electronic device including a static-random-access memory cell and a process of forming the electronic device

Split-gate non-volatile memory cell and method

Method of making a semiconductor structure useful in making a split gate non-volatile memory cell

Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device

Source/drain stressor and method therefor

Split gate nanocrystal memory integration

Method for forming a split gate device

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Memory having P-type split gate memory cells and method of operation

Split gate non-volatile memory cell with improved endurance and method therefor

Transistor with asymmetry for data storage circuitry

One transistor DRAM cell structure

Semiconductor structure with reduced gate doping and methods for forming thereof

Semiconductor device with stressors and method therefor

Electronic device including a transistor structure having an active region adjacent to a stressor layer

Engineering strain in thick strained-SOI substrates

Method for making a stressed non-volatile memory device

Split gate non-volatile memory cell with improved endurance and method therefor

WINSTEAD BRIAN A

Method of forming a split gate memory device and apparatus

Electronic device including a heterojunction region

Split gate non-volatile memory cell

Methods and systems for erase biasing of split-gate non-volatile memory cells

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Split gate memory cell with a layer of nanocrystals with improved erase performance

Semiconductor device including an active region and two layers having different stress characteristics

Semiconductor device including an active region and two layers having different stress characteristics

Method of making a non-volatile memory (NVM) cell structure

Method of making a split gate non-volatile memory (NVM) cell

LOIKO KONSTANTIN V

Split gate nanocrystal memory integration

Memory with discrete storage elements

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Split-gate non-volatile memory cells having gap protection zones

Method of making a split gate non-volatile memory (NVM) cell and a logic transistor

WHITE TED R

Split-gate non-volatile memory cell having improved overlap tolerance and method therefor

Split-gate non-volatile memory cells having improved overlap tolerance

KANG SUNG-TAEG

Nonvolatile split gate memory cell having oxide growth

Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor

HONG CHEONG M

Programming a split gate bit cell

Method of making a semiconductor structure useful in making a split gate non-volatile memory cell

BURNETT JAMES D

Method for forming one transistor DRAM cell structure

ZHANG DA

Transistors with different threshold voltages

GASQUET HORACIO P

Method for preconditioning thin film storage array for data retention

SHEN JINMIAO J

Split gate memory device with gap spacer