Inventor

GLUSCHENKOV OLEG

US230 patents

⚠️ This page may combine multiple inventors who share the name “GLUSCHENKOV OLEG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLUSCHENKOV OLEG

IBM

Structure and method to improve channel mobility by gate electrode stress modification

High acceptor level doping in silicon germanium

Structure and method for MOSFET with metallic gate electrode

Method of fabricating a field effect transistor having improved junctions

Vertical MOSFET SRAM cell

MOSFET structure with high mechanical stress in the channel

Bottom spacer formation for vertical transistor

Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric

Self aligned top extension formation for vertical transistors

On-chip electromigration monitoring system

Dual stressed SOI substrates

High performance FET with laterally thin extension

Gate electrode forming methods using conductive hard mask

Nanocircuit and self-correcting etching method for fabricating same

Temperature stable metal nitride gate electrode

Oxidation method for altering a film structure and CMOS transistor structure formed therewith

Damascene method for improved MOS transistor

Method for forming junction on insulator (JOI) structure

Method for forming high performance CMOS devices with elevated sidewall spacers

Gate stack formed with interrupted deposition processes and laser annealing

Gate stack formed with interrupted deposition processes and laser annealing

Laser anneal of buried metallic interconnects including through silicon vias

Voidless contact metal structures

Method of producing highly strained PECVD silicon nitride thin films at low temperature

Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method

Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM

Gate structure with independently tailored vertical doping profile

Trench isolation employing a doped oxide trench fill

Pitcher-shaped active area for field effect transistor and method of forming same

High performance logic and high density embedded dram with borderless contact and antispacer

Gate structure with independently tailored vertical doping profile

Method of improving gate activation by employing atomic oxygen enhanced oxidation

Method of forming low-leakage on-chip capacitor

Semi-insulating diffusion barrier for low-resistivity gate conductors

Forming gate oxides having multiple thicknesses

Method of fabricating a buried collar

Stacked vertical field-effect transistors with sacrificial layer patterning

Vertical transport field-effect transistor architecture

EUV pattern transfer with ion implantation and reduced impact of resist residue

Self aligned top extension formation for vertical transistors

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

Low resistance source drain contact formation

Bottom spacer formation for vertical transistor

Method of forming vertical transistor having dual bottom spacers

INFINEON TECHNOLOGIES AG

RTCVD process and reactor for improved conformality and step-coverage

Dual gate oxide process for uniform oxide thickness

Orientation independent oxidation of silicon

LIU YAOCHENG

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Structure and method for mobility enhanced MOSFETS with unalloyed silicide

GLUSCHENKOV OLEG

Configurable interposer