Inventor
RAPPOPORT RINAT
IL21 patents
⚠️ This page may combine multiple inventors who share the name “RAPPOPORT RINAT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS11086623B2Aug 10, 2021
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
INTEL CORP32 citations98
US11977886B2May 7, 2024
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11847452B2Dec 19, 2023
Systems, methods, and apparatus for tile configuration
INTEL CORP7 citations94
US11714642B2Aug 1, 2023
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11567765B2Jan 31, 2023
Systems, methods, and apparatuses for tile load
INTEL CORP8 citations94
US11288069B2Mar 29, 2022
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11080048B2Aug 3, 2021
Systems, methods, and apparatus for tile configuration
INTEL CORP14 citations94
US11023382B2Jun 1, 2021
Systems, methods, and apparatuses utilizing CPU storage with a memory reference
INTEL CORP14 citations84
US7865712B2Jan 4, 2011
Method and apparatus for booting a processing system
INTEL CORP13 citations84
US12536020B2Jan 27, 2026
Systems, methods, and apparatuses for tile store
INTEL CORP0 citations73
US12282773B2Apr 22, 2025
Systems, methods, and apparatus for tile configuration
INTEL CORP0 citations73
US12182571B2Dec 31, 2024
Systems, methods, and apparatuses for tile load, multiplication and accumulation
INTEL CORP0 citations73
US12147804B2Nov 19, 2024
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
INTEL CORP1 citations73
US12106100B2Oct 1, 2024
Systems, methods, and apparatuses for matrix operations
INTEL CORP0 citations73
US9727345B2Aug 8, 2017
Method for booting a heterogeneous system and presenting a symmetric core view
INTEL CORP3 citations72
US11275588B2Mar 15, 2022
Context save with variable save state size
INTEL CORP0 citations62
US10592421B2Mar 17, 2020
Instructions and logic to provide advanced paging capabilities for secure enclave page caches
INTEL CORP1 citations62
US10503517B2Dec 10, 2019
Method for booting a heterogeneous system and presenting a symmetric core view
INTEL CORP0 citations50