Inventor

LIOU JOUNG-WEI

TW61 patents

⚠️ This page may combine multiple inventors who share the name “LIOU JOUNG-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIOU JOUNG-WEI

TAIWAN SEMICONDUCTOR MFG CO LTD

Magnetic tunnel junction device and method of forming same

Back-end-of-line (BEOL) interconnect structure

Semiconductor devices including conductive features with capping layers and methods of forming the same

Sidewall spacer stack for magnetic tunnel junctions

Photoresist and method of formation and use

Support structure for barrier layer of semiconductor device

Interconnect system with improved low-K dielectrics

Multi-layer structure having a dense middle layer

Multi-layer structure having a dense middle layer

Gas diffuser unit, process chamber and wafer processing method

Method of back-end-of-line (BEOL) fabrication, and devices formed by the method

Photoresist and method of formation and use

Photoresist and method of formation and use

Conductive structure in semiconductor structure and method for forming the same

Semiconductor structure having high breakdown voltage etch-stop layer

Spacer scheme and method for MRAM

Spacer stack for magnetic tunnel junctions

Semiconductor structure having high breakdown voltage etch-stop layer

Spacer scheme and method for MRAM

Methods for forming a spacer stack for magnetic tunnel junctions

High breakdown voltage inter-metal dielectric layer

Multi-layer mask and method of forming same

Spacer scheme and method for MRAM

Interconnect system with improved low-k dielectrics

Multi-layer mask and method of forming same

Interlayer dielectric layer

Magnetic tunnel junction device and method of forming same

Magnetic tunnel junction device and method of forming same

Interlayer dielectric layer

Wafer processing method

Hardened interlayer dielectric layer

Low-K dielectric layer and porogen

Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures

Method of making interconnect structure

Low-K dielectric layer and porogen

High density dielectric etch-stop layer

Method for forming semiconductor device structure

Method of forming a high density dielectric etch-stop layer

TAIWAN SEMICONDUCTOR MFG

High aspect ratio gap fill application using high density plasma chemical vapor deposition

Photoresist and method of formation and use

Back-end-of-line (BEOL) interconnect structure

Hard mask for back-end-of-line (BEOL) interconnect structure

Method of making interconnect structure

Mechanism of forming semiconductor device having support structure

Apparatus and methods for low k dielectric layers

Method of and apparatus for active energy assist baking

LIOU JOUNG-WEI

Low-K dielectric layer and porogen

Yang hui-chun

Semiconductor devices including conductive features with capping layers and methods of forming the same

PENG YU-YUN

Apparatus and methods for low K dielectric layers

SHIH PO-CHENG

Interconnect structure and method for forming the same