Inventor

LAUER GEN P

US43 patents

⚠️ This page may combine multiple inventors who share the name “LAUER GEN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAUER GEN P

IBM

Structure and method to reduce shorting in STT-MRAM device

Structure and method to reduce shorting in STT-MRAM device

Structure and method to reduce shorting and process degradation in STT-MRAM devices

Enhanced coercivity in MTJ devices by contact depth control

Structure and method to reduce shorting and process degradation in STT-MRAM devices

III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology

Magnetoresistive structures with stressed layer

Magnetoresistive structures with stressed layer

Magnetic tunnel junction with post-deposition hydrogenation

Stacked planar double-gate lamellar field-effect transistor

Complementary metal-oxide silicon having silicon and silicon germanium channels

III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method

Spin torque MRAM fabrication using negative tone lithography and ion beam etching

Low degradation MRAM encapsulation process using silicon-rich silicon nitride film

Structure and method to reduce shorting and process degradation in stt-MRAM devices

Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET

Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET

Structure and method to reduce shorting and process degradation in STT-MRAM devices

Reduced process degradation of spin torque magnetoresistive random access memory

Structure and method to reduce shorting in STT-MRAM device

III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology

Spin torque MRAM fabrication using negative tone lithography and ion beam etching

Enhanced coercivity in MTJ devices by contact depth control

Structure and method to reduce shorting in STT-MRAM device

Complementary metal-oxide silicon having silicon and silicon germanium channels

Enhanced coercivity in MTJ devices by contact depth control

Enhanced coercivity in MTJ devices by contact depth control

Stacked planar double-gate lamellar field-effect transistor

Stacked planar double-gate lamellar field-effect transistor

Stacked planar double-gate lamellar field-effect transistor

Structure and method to reduce shorting in STT-MRAM device

Low temperature encapsulation for magnetic tunnel junction

Complementary metal-oxide silicon having silicon and silicon germanium channels

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Spin torque MRAM fabrication using negative tone lithography and ion beam etching

High-rate chemical vapor etch of silicon substrates

BRIGHTSKY MATTHEW J

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

GLOBALFOUNDRIES INC

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Low temperature salicide for replacement gate nanowires