Inventor

GRUPP DANIEL E

US41 patents

⚠️ This page may combine multiple inventors who share the name “GRUPP DANIEL E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRUPP DANIEL E

ACORN TECH INC

Insulated gate field effect transistor having passivated Schottky barriers to the channel

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Transistor with workfunction-induced charge layer

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Electrostatically operated tunneling transistor

Insulated gate field effect transistor having passivated schottky barriers to the channel

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Insulated gate field effect transistor having passivated schottky barriers to the channel

Insulated gate field-effect transistor having III-VI source/drain layer(s)

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Electrostatically operated tunneling transistor

ACORN SEMI LLC

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

HEMEX HEALTH INC

Diagnostics systems and methods

Diagnostics systems and methods

Diagnostics systems and methods

Diagnostics systems and methods

Diagnostics systems and methods

GRUPP DANIEL E

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

NEC RESEARCH INST INC

Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography

Method for fabricating free-standing thin metal films

FAULKNER CARL M

Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)