Inventor

CONNELLY DANIEL J

US38 patents

⚠️ This page may combine multiple inventors who share the name “CONNELLY DANIEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CONNELLY DANIEL J

ACORN TECH INC

Insulated gate field effect transistor having passivated Schottky barriers to the channel

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Transistor with workfunction-induced charge layer

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer

Insulated gate field effect transistor having passivated schottky barriers to the channel

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Insulated gate field effect transistor having passivated schottky barriers to the channel

Strained semiconductor using elastic edge relaxation, a buried stressor layer and a sacrificial stressor layer

Insulated gate field-effect transistor having III-VI source/drain layer(s)

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Insulated gate field effect transistor having passivated schottky barriers to the channel

Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layer

Insulated gate field effect transistor having passivated schottky barriers to the channel

ACORN SEMI LLC

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

GRUPP DANIEL E

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

FAULKNER CARL M

Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)

GOEBEL ANDREAS

Field effect transistor source or drain with a multi-facet surface

CLIFTON PAUL

Channel strain induced by strained metal in FET source or drain