Inventor

JONES ANDREW MICHAEL

GB40 patents

⚠️ This page may combine multiple inventors who share the name “JONES ANDREW MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JONES ANDREW MICHAEL

SGS THOMSON MICROELECTRONICS

Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port

System and method for on-chip communication

Method and system for transmitting interrupts from a peripheral device to another device in a computer system

Adapter for a microprocessor

Microcomputer having address diversion means for remapping an on-chip device to an external port

System and method for booting a computer

Shared memory bus arbitration system to improve access speed when accessing the same address set

System and method for remotely executing code

Microprocessor having addressable communication port

Processing system

Microcomputer chips with interconnected address and data paths

System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry

Microcomputer with interrupt packets

Microcomputer with bit packets for interrupts, control and memory access

Microcomputer with packet translation for event packets and memory access packets

Cache coherency mechanism

Interrupt and control packets for a microcomputer

Cyclic redundancy check in a computer system

JONES ANDREW MICHAEL

Cache memory system including selectively accessible pre-fetch memory for pre-fetch of variable size data

Integrated circuit package with multiple dies and a multiplexed communications interface

Integrated circuit package with multiple dies and a synchronizer

Multiple purpose integrated circuit

Integrated circuit package with multiple dies and queue allocation

Integrated circuit package with multiple dies and sampled control signals

Integrated circuit package with multiple dies and interrupt processing

Cache pre-fetching responsive to data availability

Cache memory system

IC with boot transaction translation and related methods

Cache memory controller

Integrated circuit system providing enhanced communications between integrated circuit dies and related methods

Arrangement

Integrated circuit package with multiple dies and bundling of control signals

ST MICROELECTRONICS RES & DEV

Integrated circuit package with multiple dies and a multiplexed communications interface

Circuit security

RYAN STUART

Cache arrangement

Circuit

SIEMENS AG

Method for operation of a bus system for highly flexible and quick data transmission between units connected to the bus system and configuration for carrying out the method

ST MICROELECTRONICS LTD

Multiple purpose integrated circuit

ST MICROELECTRONICS GRENOBLE 2

Method and apparatus for interfacing multiple dies with mapping for source identifier allocation

URZI IGNAZIO ANTONINO

Method and apparatus for interfacing multiple dies with mapping to modify source identity