Inventor

HSU STEVEN K

US44 patents

⚠️ This page may combine multiple inventors who share the name “HSU STEVEN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU STEVEN K

INTEL CORP

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Multiple voltage mode pre-charging and selective level shifting

Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors

Low-power search line circuit encoding technique for content addressable memories

Static random access memory with symmetric leakage-compensated bit line

Register files and caches with digital sub-threshold leakage current calibration

Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports

Full-swing source-follower leakage tolerant dynamic logic

Dynamic logic with adaptive keeper

Low clock swing latch for dual-supply voltage design

Level converting latch

Robust variable keeper strength process-compensated dynamic circuit and method

Current mirror based multi-channel leakage current monitor circuit and method

Wide voltage range level shifter with symmetrical switching

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Ultra low voltage and minimum operating voltage tolerant register file

Voltage-level converter

Low leakage and leakage tolerant stack free multi-ported register file

Leakage-tolerant memory arrangements

Double data rate dynamic logic

Shared keeper and footer flip-flop

Integrated clock gate circuit with embedded NOR

Shared keeper and footer flip-flop

Current mirror multi-channel leakage current monitor circuit and method

Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation

Pseudo-static single-ended cache cell

Variable virtual ground domino logic with leakage control

Time borrowing flip-flop with clock gating scan multiplexer

Register file with a selectable keeper circuit

Leakage tolerant register file

Fused voltage level shifting latch

Memory with spatially encoded data storage

Multi read port bit line

Active leakage control in single-ended full-swing caches

Vectored flip-flop

Vectored flip-flop

Time borrowing flip-flop with clock gating scan multiplexer

Transition-encoder sense amplifier

Aging tolerant register file

Low clock supply voltage interruptible sequential

Flop repeater circuit

HSU STEVEN K

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Voltage level shift with interim-voltage-controlled contention interrupt

MATHEW SANU

Multiplier product generation based on encoded data from addressable location