P

Inventor

RAHHAL-ORABI NADIA M

US22 patents
⚠️ This page may combine multiple inventors who share the name “RAHHAL-ORABI NADIA M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

19 patents
US9508821B2Nov 29, 2016

Self-aligned contacts

INTEL CORP13 citations92
US11887891B2Jan 30, 2024

Self-aligned contacts

INTEL CORP2 citations84
US10930557B2Feb 23, 2021

Self-aligned contacts

INTEL CORP2 citations84
US10141226B2Nov 27, 2018

Self-aligned contacts

INTEL CORP2 citations84
US9508796B2Nov 29, 2016

Internal spacers for nanowire transistors and method of fabrication thereof

INTEL CORP9 citations82
US7314836B2Jan 1, 2008

Enhanced nitride layers for metal oxide semiconductors

INTEL CORP12 citations79
US10580865B2Mar 3, 2020

Transistor with a sub-fin dielectric region under a gate

INTEL CORP2 citations73
US10461082B2Oct 29, 2019

Well-based integration of heteroepitaxial N-type transistors with P-type transistors

INTEL CORP2 citations73
US10431690B2Oct 1, 2019

High electron mobility transistors with localized sub-fin isolation

INTEL CORP3 citations73
US9935205B2Apr 3, 2018

Internal spacers for nanowire transistors and method of fabrication thereof

INTEL CORP3 citations71
US12266571B2Apr 1, 2025

Self-aligned contacts

INTEL CORP0 citations62
US11600524B2Mar 7, 2023

Self-aligned contacts

INTEL CORP0 citations62
US11631737B2Apr 18, 2023

Ingaas epi structure and wet etch process for enabling III-v GAA in art trench

INTEL CORP0 citations52
US11205707B2Dec 21, 2021

Optimizing gate profile for performance and gate fill

INTEL CORP0 citations52
US10629483B2Apr 21, 2020

Self-aligned contacts

INTEL CORP0 citations52
US9929273B2Mar 27, 2018

Apparatus and methods of forming fin structures with asymmetric profile

INTEL CORP1 citations52
US9892967B2Feb 13, 2018

Self-aligned contacts

INTEL CORP0 citations52
US9305771B2Apr 5, 2016

Prevention of metal loss in wafer processing

INTEL CORP0 citations43
US10797150B2Oct 6, 2020

Differential work function between gate stack metals to reduce parasitic capacitance

INTEL CORP0 citations42

BOHR MARK T

2 patents

WALLACE CHARLES H

1 patent