Inventor

PARKS TERRY J

US40 patents

⚠️ This page may combine multiple inventors who share the name “PARKS TERRY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARKS TERRY J

DELL USA LP

Liquid crystal display with integrated frame buffer

Inductive coupling system for power and data transfer

Disk drive controller accepting first commands for accessing composite drives and second commands for individual diagnostic drive control wherein commands are transparent to each other

Incremental search content addressable memory for increased data compression efficiency

Dual path memory retrieval system for an interleaved dynamic RAM memory unit

Multiple function interface device for option card

Display scrolling system for personal digital assistant

Random access memory power management system

System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities

Positioning device reporting X, Y and yaw motion

Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests

Method and apparatus for refreshing a selected portion of a dynamic random access memory

Redundant memory channel array configuration with data striping and error correction capabilities

Digital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuit

Method and apparatus for simplified video monitor control

Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order

Interface circuit having zero latency buffer memory and cache memory information transfer

Combined multiprocessor interrupt controller and interprocessor communication mechanism

System for memory table cache reloads in a reduced number of cycles using a memory controller to set status bits in the main memory table

Apparatus and method for optimal error correcting code to parity conversion

Method for interleaving computer disk data input-out transfers with permuted buffer addressing

Multi-purpose usage of transaction backoff and bus architecture supporting same

Configurable interface for routing data between mismatched devices

Method and apparatus for simplified control of a video monitor

Processor that performs memory access in parallel with cache access

Method and apparatus for simultaneous operation of two IDE disk drives

Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference

System and method for memory mapping

Store queue including a byte order tracking mechanism for maintaining data coherency

System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus

Method and apparatus for synchronous bus interface optimization

Apparatus and method for optimal error correcting code to parity conversion

Liquid crystal display device with octagonal cell providing increased wiring density

Processor and cache controller interface lock jumper

Apparatus for queing and storing data writes into valid word patterns

Method and apparatus for reducing partial write latency in redundant disk arrays

Method and apparatus for state machine optimization using device delay characteristics

DELL USA CORP

System for scheduling read ahead operations if new request is sequential of last n last read requests wherein n is different on independent activities

On-chip integrated circuit speed selection

IBM

Electromagnetic touch sensor input system in a cathode ray tube display device