Inventor

PEIDOUS IGOR

US54 patents

⚠️ This page may combine multiple inventors who share the name “PEIDOUS IGOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PEIDOUS IGOR

GLOBALWAFERS CO LTD

High resistivity single crystal silicon ingot and wafer having improved mechanical strength

High resistivity SOI wafers and a method of manufacturing thereof

High resistivity SOI wafers and a method of manufacturing thereof

Semiconductor on insulator structure comprising a buried high resistivity layer

Methods for assessing semiconductor structures

High resistivity silicon-on-insulator substrate comprising an isolation region

High resistivity semiconductor-on-insulator wafer and a method of manufacture

High resistivity SOI wafers and a method of manufacturing thereof

Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate

Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

Semiconductor on insulator structure comprising a buried high resistivity layer

High resistivity single crystal silicon ingot and wafer having improved mechanical strength

High resistivity single crystal silicon ingot and wafer having improved mechanical strength

Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate

Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition

ADVANCED MICRO DEVICES INC

Stress enhanced MOS transistor and methods for its fabrication

Stressed MOS device and method for its fabrication

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Methods for fabricating a stressed MOS device

Methods for fabricating a CMOS device including silicide contacts

Methods for fabrication of a stressed MOS device

Field effect transistors and methods for fabricating the same

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Stress enhanced transistor and methods for its fabrication

Stressed MOS device

Stressed MOS device and methods for its fabrication

Stress enhanced transistor

SUNEDISON SEMICONDUCTOR LTD UEN201334164H

Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition

Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

High resistivity silicon-on-insulator substrate comprising an isolation region

High resistivity silicon-on-insulator substrate comprising an isolation region

Methods for assessing semiconductor structures

SUNEDISON SEMICONDUCTOR LTD

High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface

High resistivity SOI wafers and a method of manufacturing thereof

Semiconductor on insulator structure comprising a buried high resistivity layer

SUNEDISON SEMICONDUCTOR LTD (UEN201334164H)

Process flow for manufacturing semiconductor on insulator structures in parallel

Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition

GLOBALFOUNDRIES INC

Methods for fabricating a stressed MOS device

Methods for fabricating low contact resistance CMOS circuits

CHARTERED SEMICONDUCTOR MFG

Method of filling shallow trenches

PEIDOUS IGOR

Integrated circuit employing variable thickness film

PATZ RYAN JAMES

Method for fabricating interconnect structures for semiconductor devices

IBM

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

APPLIED MATERIALS INC

Methods for fabricating dual material gate in a semiconductor device

SILFEX INC

Crucible for casting near-net shape (NNS) silicon