Inventor
NAOR EYAL
IL19 patents
Patents
19 patentsUS10929142B2Feb 23, 2021
Making precise operand-store-compare predictions to avoid false dependencies
IBM3 citations70
US10970214B2Apr 6, 2021
Selective downstream cache processing for data access
IBM0 citations62
US10956328B2Mar 23, 2021
Selective downstream cache processing for data access
IBM0 citations62
US11907124B2Feb 20, 2024
Using a shadow copy of a cache in a cache hierarchy
IBM0 citations61
US10977040B2Apr 13, 2021
Heuristic invalidation of non-useful entries in an array
IBM1 citations60
US10360030B2Jul 23, 2019
Efficient pointer load and format
IBM0 citations52
US10353707B2Jul 16, 2019
Efficient pointer load and format
IBM0 citations52
US10169041B1Jan 1, 2019
Efficient pointer load and format
IBM0 citations52
US10417127B2Sep 17, 2019
Selective downstream cache processing for data access
IBM0 citations51
US10409724B2Sep 10, 2019
Selective downstream cache processing for data access
IBM0 citations51
US11144321B2Oct 12, 2021
Store hit multiple load side register for preventing a subsequent store memory violation
IBM0 citations50
US10691604B2Jun 23, 2020
Minimizing cache latencies using set predictors
IBM0 citations50
US10684951B2Jun 16, 2020
Minimizing cache latencies using set predictors
IBM0 citations50
US11157281B2Oct 26, 2021
Prefetching data based on register-activity patterns
IBM0 citations48
US11029950B2Jun 8, 2021
Reducing latency of common source data movement instructions
IBM0 citations48
US10678549B2Jun 9, 2020
Executing processor instructions using minimal dependency queue
IBM0 citations48
US10572624B2Feb 25, 2020
Modified design debugging using differential trace back
IBM0 citations38
US10649777B2May 12, 2020
Hardware-based data prefetching based on loop-unrolled instructions
IBM0 citations37
US10324815B2Jun 18, 2019
Error checking of a multi-threaded computer processor design under test
IBM0 citations30