Inventor
PUVVADA VENUGOPAL
IN3 patents
Patents
3 patentsUS7324914B2Jan 29, 2008
Timing closure for system on a chip using voltage drop based standard delay formats
TEXAS INSTRUMENTS INC10 citations77
US7315992B2Jan 1, 2008
Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
TEXAS INSTRUMENTS INC15 citations76
US7197730B1Mar 27, 2007
Reducing time to design integrated circuits including performing electro-migration check
TEXAS INSTRUMENTS INC3 citations53