Inventor

SHEN HUGH

US107 patents

⚠️ This page may combine multiple inventors who share the name “SHEN HUGH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEN HUGH

IBM

Translation entry invalidation in a multithreaded data processing system

Processor and data processing system employing a variable store gather window

Method for priority scheduling and priority dispatching of store conditional operations in a store queue

Processor, method, and data processing system employing a variable store gather window

Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted

Method for cache correction using functional tests translated to fuse repair

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Translation entry invalidation in a multithreaded data processing system

Expedited servicing of store operations in a data processing system

Synchronizing access to data in shared memory

Synchronizing access to data in shared memory

System and method for completing updates to entire cache lines with address-only bus operations

System and method of re-ordering store operations within a processor

System and method to stall dispatch of gathered store operations in a store queue using a timer

Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model

Cache configured to log addresses of high-availability data via a non-blocking channel

Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations

Data processing system, processor and method of data processing that support memory access according to diverse memory models

Synchronizing access to shared memory by extending protection for a target address of a store-conditional request

Adaptively enabling and disabling snooping bus commands

Processing a sequence of translation entry invalidation requests with regard to draining a processor core

Translation entry invalidation in a multithreaded data processing system

Synchronized access to shared memory by extending protection for a store target address of a store-conditional request

Translation entry invalidation in a multithreaded data processing system

Translation entry invalidation in a multithreaded data processing system

Expedited servicing of store operations in a data processing system

Expedited servicing of store operations in a data processing system

Expedited servicing of store operations in a data processing system

Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Topology specific replicated bus unit addressing in a data processing system

Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration

Concurrent processing of translation entry invalidation requests in a processor core

Initiating interconnect operation without waiting on lower level cache directory lookup

Cache snooping mode extending coherence protection for certain requests

Efficient system bootstrap loading

Completion logic performing early commitment of a store-conditional access based on a flag

Cache-inhibited write operations

Zeroing a memory block without processor caching

Managing speculative memory access requests in the presence of transactional storage accesses

Adaptively enabling and disabling snooping fastpath commands

Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Bypassing a store-conditional request around a store queue

Variable store gather window

System and method for completing full updates to entire cache lines stores with address-only bus operations

Reducing number of rejected snoop requests by extending time to respond to snoop request

Reducing number of rejected snoop requests by extending time to respond to snoop request

ARIMILLI LAKSHMINARAYANA BABA

Processor system and methods of triggering a block move using a system bus write command initiated by user code

CUMMINGS DAVID W

Updating partial cache lines in a data processing system

GUTHRIE GUY L

Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration