Inventor
LICHTENAU CÉDRIC
DE12 patents
⚠️ This page may combine multiple inventors who share the name “LICHTENAU CÉDRIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS10649781B2May 12, 2020
Enhanced performance-aware instruction scheduling
IBM4 citations72
US10324816B2Jun 18, 2019
Checking a computer processor design for soft error handling
IBM5 citations70
US9297856B2Mar 29, 2016
Implementing MISR compression methods for test time reduction
IBM2 citations62
US10684861B2Jun 16, 2020
Enhanced performance-aware instruction scheduling
IBM0 citations51
US9959093B2May 1, 2018
Binary fused multiply-add floating-point calculations
IBM1 citations51
US9952829B2Apr 24, 2018
Binary fused multiply-add floating-point calculations
IBM0 citations51
US10552167B2Feb 4, 2020
Clock-gating for multicycle instructions
IBM0 citations49
US10318395B2Jun 11, 2019
Checking a computer processor design for soft error handling
IBM0 citations49
US9977680B2May 22, 2018
Clock-gating for multicycle instructions
IBM1 citations49
US10275391B2Apr 30, 2019
Combining of several execution units to compute a single wide scalar result
IBM0 citations40
US9734126B1Aug 15, 2017
Post-silicon configurable instruction behavior based on input operands
IBM0 citations40