Inventor

XIONG CHENRONG

US70 patents

⚠️ This page may combine multiple inventors who share the name “XIONG CHENRONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XIONG CHENRONG

SK HYNIX INC

Deep learning based regression framework for read thresholds in a NAND flash memory

Error mitigation scheme for bit-flipping decoders for irregular low-density parity-check codes

Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes

Data storage device

Data storage device

Memory system with decoders and method of operating such memory system and decoders

Deep learning for low-density parity-check (LDPC) decoding

Fast-converging bit-flipping decoder for low-density parity-check codes

Early termination of low-density parity-check (LDPC) decoding

Data storage device

Storage device performance optimization using deep learning

Memory system and method for read operation based on grouping of word lines

Memory system for multi-clustering read thresholds and method thereof

Data storage device

Fast fail support for error correction in non-volatile memory

Error characteristic estimation for NAND flash

Neighbor assisted correction error recovery for memory system and method thereof

Encoder for memory system and method thereof

Memory system and method for optimizing read threshold

Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage

Min-sum decoding for LDPC codes

Memory system and method for bad block management

Dynamic interleaver change for bit line failures in NAND flash storage

Memory system with on-the-fly error detection and termination and operating method thereof

Low-complexity LDPC encoder

Symbol-based coding for NAND flash devices

Memory system having feature boosting and operating method thereof

Memory system of optimal read reference voltage and operating method thereof

Bit-flipping LDPC decoding algorithm with hard channel information

Soft chip-kill recovery for multiple wordlines failure

Memory system with hybrid iterative decoding capability and method of operating such memory system

Decoder for memory system and method thereof

Encoder and decoder for memory system and method thereof

Memory system with super chip-kill recovery and method of operating such memory system

Memory system with soft-read suspend scheme and method of operating such memory system

Soft chip-kill recovery for multiple wordlines failure

Memory system with LDPC decoder and method of operating such memory system and LDPC decoder

Memory system with adaptive read-threshold scheme and method of operating such memory system

Memory system with low-latency read recovery and method of operating the memory system

Quality of service (QoS) aware data storage decoder

Soft-input soft-output component code decoder for generalized low-density parity-check codes

INNOGRIT TECHNOLOGIES CO LTD

Bit-flipping method for decoding LDPC code and system using the same

Soft decoding correctable page assisted LLR estimation

Error recovery using adaptive LLR lookup table

Concatenated error correcting codes

Reference voltage adjustment based on post-decoding and pre-decoding state information

Concatenated error correcting codes

Error recovery using adaptive LLR lookup table

Reference voltage adjustment based on post-decoding and pre-decoding state information

Systems and methods for decoding codewords