Inventor
REYER KENNETH J
US16 patents
⚠️ This page may combine multiple inventors who share the name “REYER KENNETH J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
15 patentsUS7064990B1Jun 20, 2006
Method and apparatus for implementing multiple column redundancy for memory
IBM29 citations92
US7471590B2Dec 30, 2008
Write control circuitry and method for a memory array configured with multiple memory subarrays
IBM11 citations84
US7283417B2Oct 16, 2007
Write control circuitry and method for a memory array configured with multiple memory subarrays
IBM8 citations73
US7176725B2Feb 13, 2007
Fast pulse powered NOR decode apparatus for semiconductor devices
IBM9 citations73
US7099206B2Aug 29, 2006
High density bitline selection apparatus for semiconductor memory devices
IBM7 citations73
US10943647B1Mar 9, 2021
Bit-line mux driver with diode header for computer memory
IBM5 citations71
US10930339B1Feb 23, 2021
Voltage bitline high (VBLH) regulation for computer memory
IBM3 citations68
US9025403B1May 5, 2015
Dynamic cascode-managed high-voltage word-line driver circuit
IBM2 citations62
US7688650B2Mar 30, 2010
Write control method for a memory array configured with multiple memory subarrays
IBM2 citations62
US7299374B2Nov 20, 2007
Clock control method and apparatus for a memory array
IBM2 citations62
US7068554B1Jun 27, 2006
Apparatus and method for implementing multiple memory redundancy with delay tracking clock
IBM4 citations62
US9748958B2Aug 29, 2017
Dynamic high voltage driver with adjustable clamped output level
IBM0 citations51
US9053770B1Jun 9, 2015
Dynamic cascode-managed high-voltage word-line driver circuit
IBM0 citations51
US7380191B2May 27, 2008
ABIST data compression and serialization for memory built-in self test of SRAM with redundancy
IBM1 citations51
US7170320B2Jan 30, 2007
Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering
IBM1 citations51