Inventor

DASTIDAR JAIDEEP

US54 patents

⚠️ This page may combine multiple inventors who share the name “DASTIDAR JAIDEEP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DASTIDAR JAIDEEP

XILINX INC

Adaptive integrated programmable device platform

Adaptive integrated programmable device platform

Machine learning model updates to ML accelerators

Domain assist processor-peer for coherent acceleration

Machine learning model updates to ML accelerators

Routing network using global address map with adaptive main memory expansion for a plurality of home agents

Scalable coherence management independent of transport protocol

Transparent port aggregation in multi-chip transport protocols

Spatial distribution in a 3D data processing unit

Routing network using global address map with adaptive main memory expansion for a plurality of home agents

Logical transport overlayed over a physical transport having a tree topology

Cache coherent acceleration function virtualization

Fine-grained multi-tenant cache management

Domain aware data migration in coherent heterogenous systems

Multiple protocol layer conversion

Scratchpad memory management in a computing system

Machine learning model updates to ML accelerators

Routing network using global address map with adaptive main memory expansion for a plurality of home agents

Cache coherent acceleration function virtualization with hierarchical partition hardware circuity in accelerator

Fine-grained multi-tenant cache management

Hybrid hardware-software coherent framework

Hardware coherent computational expansion memory

Disaggregated switch control path with direct-attached dispatch

Compressed tag coherency messaging

Producer-to-consumer active direct cache transfers

Delegated snoop protocol

Secure shell and role isolation for multi-tenant compute

Adaptive integrated programmable device platform

Spatial distribution in a 3D data processing unit

Multi-tenant aware data processing units

Zoned accelerator embedded processing

Adaptive integrated programmable data processing unit

Adaptive integrated programmable device platform

Synchronization of system resources in a multi-socket data processing system

Efficiency and quality of service improvements for systems with higher bandwidth clients mixed with lower bandwidth clients

Adaptive acceleration of transport layer security

Multipath memory with static or dynamic mapping to coherent or MMIO space

Peripheral I/O device with assignable I/O and coherent domains

Transparent port aggregation in multi-chip transport protocols

APPLE INC

Systems and methods for controlling data on a bus using latency

Systems and methods for scheduling different types of memory requests with varying data sizes

Systems and methods for maintaining specific ordering in bus traffic

Systems and methods for arbitrating traffic in a bus

Systems and methods for arbitrating traffic in a bus

Systems and methods for providing a back pressure free interconnect

HEWLETT PACKARD DEVELOPMENT CO

System to optimally order cycles originating from a single physical link

Inter-queue ordering mechanism

Method and apparatus for a dual mode PCI/PCI-X device

DESHPANDE SANJAY

Access management technique with operation translation capability

FREESCALE SEMICONDUCTOR INC

System and method for enabling maximum performance operation within an extended ambient temperature range