Inventor

MITTAL MILLIND

US164 patents

⚠️ This page may combine multiple inventors who share the name “MITTAL MILLIND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MITTAL MILLIND

INTEL CORP

Method and apparatus for secure execution using a secure memory partition

Controlling access to multiple isolated memories in an isolated execution environment

Controlling access to multiple memory zones in an isolated execution environment

Processor executing unpack instruction to interleave data elements from two packed data

Executing isolated mode instructions in a secure system running in privilege rings

Method for performing multiply-add operations on packed data

Method for unpacking a plurality of packed data into a result packed data

Microprocessor capable of unpacking packed data

Method and apparatus for performing multiply-subtract operations on packed data

Performance throttling to reduce IC power consumption

Method and apparatus for performing multiply-add operations on packed data

Protecting software environment in isolated execution

Platform and method for issuing and certifying a hardware-protected attestation key

Generating a key hieararchy for use in an isolated execution environment

Method of sorting numbers to obtain maxima/minima values with ordering

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction

Method for packing a plurality of packed data elements in response to a pack instruction

Processor performing packed data multiplication

Method for performing shift operations on packed data

Microprocessor capable of unpacking packed data in response to a unpack instruction

Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor

Apparatus for performing multiply-add operations on packed data

Apparatus for performing multiply-add operations on packed data

Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file

Method and apparatus for performing multiply and accumulate operations on packed data

Method and apparatus for secure execution using a secure memory partition

Managing a secure environment using a chipset in isolated execution mode

Platform and method for remote attestation of a platform

Controlling accesses to isolated memory using a memory controller for isolated execution

Apparatus for performing packed shift operations

Apparatus for performing packed shift operations

Method for executing instructions that operate on different data types stored in the same single logical register file

System for signal processing using multiply-add operations

Emptying packed data state during execution of packed data instructions

Computer implemented method for transferring packed data between register files and memory

Controlling shared memory access ordering in a multi-processing system using an acquire/release consistency model

Processor for performing shift operations on packed data

Executing different instructions that cause different data type operations to be performed on single logical register file

Method for multiplying packed data

Method and apparatus for hardware platform identification with privacy protection

Method and apparatus for secure execution using a secure memory partition

Method and apparatus for secure execution using a secure memory partition

ALACRITECH INC

Native copy instruction for file-access processor with copy-rule-based validation

Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests

Native lookup instruction for file-access processor searching a three-level lookup cache for variable-length keys

ENGINES INC X

Deterministic lookup using hashed key in a multi-stride compressed trie structure

OPTIM NETWORKS

Method and apparatus for end to end forwarding architecture

INST THE DEV OF EMERGING ARCHI

Computer system that provides atomicity by using a tlb to indicate whether an exportable instruction should be executed using cache coherency or by exporting the exportable instruction, and emulates instructions specifying a bus lock

XILINX INC

Machine learning model updates to ML accelerators