Inventor
OKADA DAVID N
US21 patents
⚠️ This page may combine multiple inventors who share the name “OKADA DAVID N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GREAT WALL SEMICONDUCTOR CORP
11 patentsUS7842568B2Nov 30, 2010
Lateral power semiconductor device for high frequency power conversion system, has isolation layer formed over substrate for reducing minority carrier storage in substrate
GREAT WALL SEMICONDUCTOR CORP43 citations92
US7605435B2Oct 20, 2009
Bi-directional MOSFET power switch with single metal layer
GREAT WALL SEMICONDUCTOR CORP9 citations83
US9640638B2May 2, 2017
Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON
GREAT WALL SEMICONDUCTOR CORP4 citations72
US9299774B2Mar 29, 2016
Device structure and methods of forming superjunction lateral power MOSFET with surrounding LDD
GREAT WALL SEMICONDUCTOR CORP2 citations62
US7800223B2Sep 21, 2010
Chip-scale monolithic load switch for portable applications
GREAT WALL SEMICONDUCTOR CORP2 citations62
US7612418B2Nov 3, 2009
Monolithic power semiconductor structures including pairs of integrated devices
GREAT WALL SEMICONDUCTOR CORP3 citations62
US10199459B2Feb 5, 2019
Superjunction with surrounding lightly doped drain region
GREAT WALL SEMICONDUCTOR CORP0 citations51
US7649247B2Jan 19, 2010
Radiation hardened lateral MOSFET structure
GREAT WALL SEMICONDUCTOR CORP0 citations51
US7432595B2Oct 7, 2008
System and method to reduce metal series resistance of bumped chip
GREAT WALL SEMICONDUCTOR CORP1 citations51
US10707327B2Jul 7, 2020
MOSFET with reduced resistance
GREAT WALL SEMICONDUCTOR CORP0 citations41
US9018706B2Apr 28, 2015
Monolithic MOSFET and Schottky diode for mobile phone boost converter
GREAT WALL SEMICONDUCTOR CORP0 citations41
MOTOROLA INC
3 patentsUS5294824AMar 15, 1994
High voltage transistor having reduced on-resistance
MOTOROLA INC248 citations98
US5032878AJul 16, 1991
High voltage planar edge termination using a punch-through retarding implant
MOTOROLA INC33 citations92
US4966858AOct 30, 1990
Method of fabricating a lateral semiconductor structure including field plates for self-alignment
MOTOROLA INC18 citations72
SHEN ZHENG JOHN
2 patentsUS9099519B2Aug 4, 2015
Semiconductor device and method of forming junction enhanced trench power MOSFET
SHEN ZHENG JOHN7 citations82
US8962425B2Feb 24, 2015
Semiconductor device and method of forming junction enhanced trench power MOSFET having gate structure embedded within trench
SHEN ZHENG JOHN7 citations82
ANDERSON SAMUEL J
2 patentsUS9006099B2Apr 14, 2015
Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump
ANDERSON SAMUEL J6 citations70
US8895430B2Nov 25, 2014
Method of making a semiconductor device comprising a land grid array flip chip bump system with short bumps
ANDERSON SAMUEL J1 citations43