Inventor

MEIER NATHANIEL J

US46 patents

⚠️ This page may combine multiple inventors who share the name “MEIER NATHANIEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEIER NATHANIEL J

MICRON TECHNOLOGY INC

Apparatuses and methods for staggered timing of targeted refresh operations

Apparatuses and methods for tracking victim rows

Methods for row hammer mitigation and memory devices and systems employing the same

Apparatuses and methods for staggered timing of skipped refresh operations

Apparatuses and methods for dynamic refresh allocation

Apparatuses and methods for lossy row access counting

Apparatuses and methods for controlling steal rates

Apparatuses and methods for tracking victim rows

Apparatuses and methods for staggered timing of skipped refresh operations

Apparatuses and methods for staggered timing of targeted refresh operations

Semiconductor device with secure access key and associated methods and systems

Apparatuses and methods for controlling steal rates

Apparatuses and methods for dynamic refresh allocation

Semiconductor device with secure access key and associated methods and systems

Apparatuses including test segment circuits having latch circuits for testing a semiconductor die

Refresh and access modes for memory

Apparatus with refresh management mechanism

Refresh and access modes for memory

Semiconductor device with secure access key and associated methods and systems

Semiconductor device with secure access key and associated methods and systems

Row access strobe (RAS) clobber and row hammer failure mitigation

Row access strobe (RAS) clobber and row hammer failures using a deterministic protocol

Semiconductor device with self-lock security and associated methods and systems

Mediating directed refresh management induced row hammer and row access strobe (RAS) clobber failures

Illegal operation reaction at a memory device

Semiconductor device with secure access key and associated methods and systems

Semiconductor devices with security lock and associated methods and systems

Semiconductor device with self-lock security and associated methods and systems

Segmented digital die ring

Refresh command management

Apparatuses including test segment circuits having latch circuits for testing a semiconductor die

Apparatus with a security mechanism and methods for operating the same

Memory with automatic background precondition upon powerup

Memory with automatic background precondition upon powerup

Host refresh control

Apparatuses, systems, and methods for controller directed targeted refresh operations based on sampling command

Dynamic address scramble

LODESTAR LICENSING GROUP LLC

Methods for row hammer mitigation and memory devices and systems employing the same

Apparatus with refresh management mechanism

Apparatus with refresh management mechanism

Semiconductor device with secure access key and associated methods and systems

Methods for row hammer mitigation and memory devices and systems employing the same

Semiconductor device with secure access key and associated methods and systems

Semiconductor device with secure access key and associated methods and systems

Refresh and access modes for memory

Semiconductor device with secure access key and associated methods and systems