Inventor

AGARWAL ISHWAR

US44 patents

⚠️ This page may combine multiple inventors who share the name “AGARWAL ISHWAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AGARWAL ISHWAR

INTEL CORP

System, apparatus and method for processing remote direct memory access operations with a device-attached memory

Multichip package link

High bandwidth link layer for coherent messages

PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory

Method, apparatus, system for optimized work submission to an accelerator work queue

Non-posted write transactions for a computer bus

Changing cache ownership in clustered multiprocessor

Persistent memory write semantics on PCIe with existing TLP definition

System, apparatus and method for increasing efficiency of link communications

High bandwidth link layer for coherent messages

Non-posted write transactions for a computer bus

Method, apparatus, system for early page granular hints from a PCIe device

Non-posted write transactions for a computer bus

Method, apparatus, system for early page granular hints from a PCIe device

Techniques to provide cache coherency based on cache type

System, apparatus and method for communicating telemetry information via virtual bus encodings

Circuits and methods for coherent writing to host systems

Techniques to support mulitple interconnect protocols for an interconnect

System, apparatus and method for memory mirroring in a buffered memory architecture

Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles

Changing cache ownership in clustered multiprocessor

Method and apparatus for distributed snoop filtering

Memory pressure notifier

MICROSOFT TECHNOLOGY LICENSING LLC

Direct swap caching with zero line optimizations

Detecting and mitigating memory attacks

Detecting and mitigating memory attacks

Computing device with independently coherent nodes

Computing device with independently coherent nodes

Addressing for disaggregated memory pool

Memory operations management in computing systems

Computing device with independently coherent nodes

Paging in thin-provisioned disaggregated memory

Paging in thin-provisioned disaggregated memory

Direct swap caching with zero line optimizations

Memory tiering techniques in computing systems

Managing and ranking memory resources

Memory tiering techniques in computing systems

Managing and ranking memory resources

Addressing for disaggregated memory pool

Systems and methods with integrated memory pooling and direct swap caching

Disaggregated memory pool assignment

Confidential compute architecture integrated with direct swap caching

Direct swap caching with noisy neighbor mitigation and dynamic address range assignment

Systems and methods for flush plus reload cache side-channel attack mitigation