Inventor

TSIEN BENJAMIN

US70 patents

⚠️ This page may combine multiple inventors who share the name “TSIEN BENJAMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSIEN BENJAMIN

ADVANCED MICRO DEVICES INC

Remote hit predictor

Method of task transition between heterogenous processors

Probe filter retention based low power state

System-wide low power management

Dynamic control of multi-region fabric

Multi-node system low power management

Shared data fabric processing client reset system and method

Technique for extended idle duration for display to improve power consumption

Using islands to control operating parameters for functional blocks in an electronic device

Reducing chiplet wakeup latency

Dynamic clock control to increase stutter efficiency in the memory subsystem

Save and restore scoreboard

Method of task transition between heterogenous processors

Low power memory state during non-idle processor state

System-wide low power management

Scheduling training of an inter-chiplet interface

On-demand IP initialization within power states

Device and method for two-stage transitioning between reduced power states

Method and apparatus for managing power states

Droop mitigation for an inter-chiplet interface

Technique to enable simultaneous use of on-die SRAM as cache and memory

Device and method for efficient transitioning to and from reduced power state

Using a hardware-based controller for power state management

Probe filter retention based low power state

Demand based probe filter initialization after low power state

Device and method for efficient transitioning to and from reduced power state

Hierarchical state save and restore for device with varying power states

Arbitration scheme for coherent and non-coherent memory requests

Dynamic control of multi-region fabric

Technique for extended idle duration for display to improve power consumption

Dynamic cache bypass for power savings

Arbitrated interrupt steering in heterogeneous processors

Memory power performance state optimization during image display

Reduced mesh lane routing

On-demand regulation of memory bandwidth utilization to service requirements of display

Device and method for reducing save-restore latency using address linearization

Precise shadowing and adjustment of on-die timers in low power states

Reducing chiplet wakeup latency

Allocation control for cache

INTEL CORP

Hiding conflict, coherence completion and transaction ID elements of a coherence protocol

Ring interconnect with multiple coherence networks

Two-hop source snoop based cache coherence protocol

Two-hop source snoop based messaging protocol

Memory attribute speculation

Pre-coherence channel

Pre-coherence channel

Hiding conflict, coherence completion and transaction ID elements of a coherence protocol

Early issue of transaction ID

Interconnect transaction translation technique

BATSON BRANNON J

Two-hop source snoop based messaging protocol