Inventor

FOO YOONG-CHERT

GB66 patents

⚠️ This page may combine multiple inventors who share the name “FOO YOONG-CHERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FOO YOONG-CHERT

IMAGINATION TECH LTD

Task execution in a SIMD processing unit

Scheduling tasks using targeted pipelines

Methods and systems for inter-pipeline data hazard avoidance

Scheduling tasks using targeted pipelines

Methods and systems for inter-pipeline data hazard avoidance

Method and system for multisample antialiasing

Multi-output decoder for texture decompression

Decoder unit for texture decompression

Performance profiling in computer graphics

Allocation of tiles to processing engines in a graphics processing system

Methods and systems for inter-pipeline data hazard avoidance

Queues for inter-pipeline data hazard avoidance

Task scheduling in a GPU using wakeup event state data

Synchronizing scheduling tasks with atomic ALU

Task scheduling in a GPU

Task scheduling in a GPU

Task execution in a SIMD processing unit with parallel groups of processing lanes

Multi-output decoder for texture decompression

Methods and systems for inter-pipeline data hazard avoidance

Scheduling tasks using swap flags

Synchronizing scheduling tasks with atomic ALU

Task execution in a SIMD processing unit with parallel groups of processing lanes

Scheduling tasks using targeted pipelines

Multi-phased and multi-threaded program execution based on SIMD ratio

Scheduling tasks using work fullness counter

Multi-output decoder for texture decompression

Task execution in a SIMD processing unit with parallel groups of processing lanes

Task scheduling in a GPU using wakeup event state data

Allocation of memory resources to SIMD workgroups

Multi-output decoder for texture decompression

Decoder unit for texture decompression

Scheduling tasks using swap flags

Synchronizing scheduling tasks with atomic ALU

Task execution in a SIMD processing unit with parallel groups of processing lanes

Scheduling tasks using work fullness counter

Decoder unit for texture decompression

Allocation of memory resources to SIMD workgroups

APPLE INC

On-demand memory allocation

Color state techniques for graphics processors

Hardware support for conversion between integer and floating-point data

Preemption techniques for memory-backed registers

On-demand memory allocation

Graphics memory space for shader core

FOO YOONG CHERT

Synchronisation of execution threads on a multi-threaded processor

Synchronisation of execution threads on a multi-threaded processor

Multi-phased and multi-threaded program execution based on SIMD ratio

CANON KK

Image pattern detection method and apparatus

Sequential bus architecture

BERGLAS MORRIE

Processing long-latency instructions in a pipelined processor

Processing long-latency instructions in a pipelined processor