Inventor

PARRY JONATHAN S

US117 patents

⚠️ This page may combine multiple inventors who share the name “PARRY JONATHAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARRY JONATHAN S

MICRON TECHNOLOGY INC

Methods for independent memory bank maintenance and memory devices and systems employing the same

Apparatus with an internal-operation management mechanism

Access operation status signaling for memory systems

Dual address encoding for logical-to-physical mapping

Non-volatile memory devices and systems with volatile memory features and methods for operating the same

Methods for independent memory bank maintenance and memory devices and systems employing the same

Efficient scrambling and encoding for copyback procedures using precomputed values

Methods for independent memory bank maintenance and memory devices and systems employing the same

Methods for independent memory bank maintenance and memory devices and systems employing the same

Methods for independent memory bank maintenance and memory devices and systems employing the same

Methods for independent memory bank maintenance and memory devices and systems employing the same

Methods for detecting and mitigating memory media degradation and memory devices employing the same

Non-volatile memory devices and systems with read-only memory features and methods for operating the same

Methods for independent memory bank maintenance and memory devices and systems employing the same

Methods for independent memory bank maintenance and memory devices and systems employing the same

Dual address encoding for logical-to-physical mapping

Read prediction during a system boot procedure

Overwriting at a memory system

Non-volatile memory devices and systems with volatile memory features and methods for operating the same

Transferring memory system data to a host system

Non-volatile memory devices and systems with volatile memory features and methods for operating the same

Power architecture for non-volatile memory

Signaling mechanism for bus inversion

Dynamic power management network for memory devices

Current summing monitoring circuit in a multi-chip package to control power

Methods for detecting and mitigating memory media degradation and memory devices employing the same

Methods for detecting and mitigating memory media degradation and memory devices employing the same

Memory with non-volatile configurations for efficient power management and operation of the same

Modified read counter incrementing scheme in a memory sub-system

Topology-based retirement in a memory system

Host recovery for a stuck condition

Padding cached data with valid data for memory flush commands

Access operation status signaling for memory systems

Code rate as function of logical saturation

Using a flag to indicate whether a mapping entry points to sequentially stored data

Padding cached data with valid data for memory flush commands

Host recovery for a stuck condition

Methods for independent memory bank maintenance and memory devices and systems employing the same

Power control for boot-up of memory systems

Using incomplete super blocks for increased write performance

Host-configurable error protection

Non-volatile memory devices and systems with read-only memory features and methods for operating the same

Status information retrieval for a memory device

Volatile register to detect power loss

Dual address encoding for logical-to-physical mapping

Logical-to-physical mapping using a flag to indicate whether a mapping entry points to [[for]] sequentially stored data

Methods for detecting and mitigating memory media degradation and memory devices employing the same

Peak power management of dice in a power network

LODESTAR LICENSING GROUP LLC

Dual address encoding for logical-to-physical mapping

Methods for independent memory bank maintenance and memory devices and systems employing the same