Inventor · disambiguated record
Alexandre Andreev
Also filed as: ANDREEV ALEXANDRE · ANDREEV ALEXANDRE E
20 granted patents·296 citations·filing 2001–2012
93Inventor score
Top patents by PatentIndex Score
20 records- 0198US7093228B2Method and system for classifying an integrated circuit for optical proximity correctionLSI LOGIC CORP·Filed 2002·Granted Aug 15, 2006·221 cites·27 claims
- 0279US7389484B2Method and apparatus for tiling memories in integrated circuit layoutLSI CORP·Filed 2005·Granted Jun 17, 2008·10 cites·20 claims
- 0375US8156391B2Data controlling in the MBIST chain architectureANDREEV ALEXANDRE·Filed 2008·Granted Apr 10, 2012·8 cites·29 claims
- 0470US6845495B2Multidirectional routerLSI LOGIC CORP·Filed 2001·Granted Jan 18, 2005·15 cites·30 claims
- 0569US7424687B2Method and apparatus for mapping design memories to integrated circuit layoutLSI CORP·Filed 2005·Granted Sep 9, 2008·6 cites·19 claims
- 0668US7584442B2Method and apparatus for generating memory models and timing databaseLSI CORP·Filed 2005·Granted Sep 1, 2009·3 cites·9 claims
- 0765US8176397B2Variable redundancy reed-solomon encoderPANTELEEV PAVEL·Filed 2008·Granted May 8, 2012·7 cites·14 claims
- 0864US8245168B2Method and apparatus for generating memory models and timing databaseANDREEV ALEXANDRE·Filed 2009·Granted Aug 14, 2012·2 cites·11 claims
- 0963US7200826B2RRAM memory timing learning toolLSI LOGIC CORP·Filed 2004·Granted Apr 3, 2007·9 cites·4 claims
- 1060US6757881B2Power routing with obstaclesLSI LOGIC CORP·Filed 2002·Granted Jun 29, 2004·7 cites·27 claims
- 1158US8037432B2Method and apparatus for mapping design memories to integrated circuit layoutLSI CORP·Filed 2008·Granted Oct 11, 2011·3 cites·12 claims
- 1252US8566769B2Method and apparatus for generating memory models and timing databaseANDREEV ALEXANDRE·Filed 2012·Granted Oct 22, 2013·0 cites·13 claims
- 1351US8046643B2Transport subsystem for an MBIST chain architectureLSI CORP·Filed 2008·Granted Oct 25, 2011·2 cites·20 claims
- 1450US7155688B2Memory generation and placementLSI LOGIC CORP·Filed 2004·Granted Dec 26, 2006·1 cites·5 claims
- 1549US7949909B2Address controlling in the MBIST chain architectureLSI CORP·Filed 2008·Granted May 24, 2011·1 cites·22 claims
- 1647US7207026B2Memory tiling architectureLSI LOGIC CORP·Filed 2004·Granted Apr 17, 2007·0 cites·4 claims
- 1746US8209589B2Reed-solomon decoder with a variable number of correctable errorsANDREEV ALEXANDRE·Filed 2008·Granted Jun 26, 2012·1 cites·18 claims
- 1842US8312072B2Universal Galois field multiplierGASHKOV SERGEI B·Filed 2008·Granted Nov 13, 2012·0 cites·20 claims
- 1940US7788563B2Generation of test sequences during memory built-in self testing of multiple memoriesLSI CORP·Filed 2008·Granted Aug 31, 2010·0 cites·20 claims
- 2033US7308633B2Master controller architectureLSI CORP·Filed 2004·Granted Dec 11, 2007·0 cites·1 claims
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