Inventor

ZAMIR RAN

IL90 patents

⚠️ This page may combine multiple inventors who share the name “ZAMIR RAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZAMIR RAN

WESTERN DIGITAL TECH INC

Storage system and method for decision-based memory read threshold calibration

Adaptive soft-bit compression in flash memory

Iterative decoder performance prediction using machine learning

Non-volatile storage system with read calibration

Fast copy through controller

On-chip non-volatile memory (NVM) search

Single-port memory with opportunistic writes

Adaptive bit-flipping decoder based on dynamic error information

Redundancy data in integrated memory assembly

Data compression with entropy encoding

Non-volatile memory die with deep learning neural network

Memory matched low density parity check coding schemes

Data integrity protection with partial updates

Endurance groups ECC allocation

Soft bit reference level calibration using decoded data

Data-assisted LDPC decoding

Storage system and method for fast low-density parity check (LDPC) encoding

Adaptive usage of irregular code schemas based on specific system level triggers and policies

Generalized low-density parity-check codes

Grown defect detection and mitigation using ECC in memory systems

Storage system and method for bad block recycling

Machine learning for temperature compensation

Punctured bit estimation and bit error rate estimation

On-chip non-volatile memory (NVM) search

Optimizations for variable sector size in storage device namespaces

Storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array

Neural network data updates using in-place bit-addressable writes within storage class memory

Read threshold calibration using multiple decoders

Storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array

Generating and using a state transition matrix for decoding data in a DNA-based storage system

Error correction systems and methods for DNA storage

DNA storage error correction code architecture for optimized decoding

Calibrating state transition probabilities associated with a DNA-based storage system to optimize decoding

Memory device with reinforcement learning with Q-learning acceleration

Storage device throttling in proof of space blockchain systems

Storage media based search function for key value data storage devices

Key-to-physical table optimization for key value data storage devices

SANDISK TECHNOLOGIES LLC

Multi-channel memory operations based on bit error rates

ECC and read adjustment based on dynamic memory error model estimation

Multi-stage decoder

ECC decoder with multiple decoding modes

Column-layered message-passing LDPC decoder

Storage system and method for handling a burst of errors

Multi-type parity bit generation for encoding and decoding

Bit-order modification for different memory areas of a storage device

Decoder with parallel decoding paths

Adaptive scheduler for decoding

SANDISK TECHNOLOGIES INC

Pipelined decoder with syndrome feedback path

Disturb condition detection for a resistive random access memory

Data storage device with joint error correction code engines