Inventor

ROUSE GEORGE V

US25 patents

⚠️ This page may combine multiple inventors who share the name “ROUSE GEORGE V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROUSE GEORGE V

HARRIS CORP

Bonded wafer processing with oxidative bonding

Bonded wafer processing with metal silicidation

Bonded wafer processing with metal silicidation

Manufacturing ultra-thin wafer using a handle wafer

Bonded wafer

Bonded wafer processing

Bonded wafer processing

Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process

SOI wafer with sige

Ultra-thin circuit fabrication by controlled wafer debonding

Bonded wafer and method of fabrication thereof

Method of fabricating back diffused bonded oxide substrates

Wafer bonding process employing liquid oxidant

Manufacturing ultra-thin dielectrically isolated wafers

Dielectric isolation process using double wafer bonding

SC-2 based pre-thermal treatment wafer cleaning process

Wafer bonding using trapped oxidizing vapor

INTERSIL CORP

Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method

Bonded wafer with metal silicidation

Power trench transistor device source region formation using silicon spacer

BICMOS process with low temperature coefficient resistor (TCRL)

INTERSIL INC

BiCMOS process with low temperature coefficient resistor (TCRL)

Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone

Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone

FAIRCHILD SEMICONDUCTOR

Power trench transistor device source region formation using silicon spacer