Inventor
HAMAGUCHI KAZUMASA
JP17 patents
Patents
17 patentsUS5923339AJul 13, 1999
Higher-speed parallel processing
CANON KK74 citations96
US5860110AJan 12, 1999
Conference maintenance method for cache memories in multi-processor system triggered by a predetermined synchronization point and a predetermined condition
CANON KK55 citations96
US5381466AJan 10, 1995
Network systems
CANON KK68 citations95
US6138217AOct 24, 2000
Method and apparatus for cache coherency in an interconnecting network
CANON KK45 citations92
US6078337AJun 20, 2000
Maintaining consistency of cache memory data by arbitrating use of a connection route by plural nodes
CANON KK23 citations92
US6009490ADec 28, 1999
System having plurality of nodes with respective memories and an arbiter for performing arbitration of connection line use for transfer of data between nodes
CANON KK32 citations92
US5802295ASep 1, 1998
Information processing method and system therefor
CANON KK20 citations92
US5604748AFeb 18, 1997
Information processing apparatus for transmitting information among a plurality of nodes and arbitration method in such information processing apparatus
CANON KK26 citations92
US5602663AFeb 11, 1997
Information processing apparatus for multiplex transmission of signal for arbitration and signal for data transfer
CANON KK35 citations92
US5561542AOct 1, 1996
Optical communication system and method for performing communication under clock control
CANON KK24 citations92
US5386546AJan 31, 1995
Block substitution method in a cache memory of a multiprocessor system
CANON KK25 citations92
US5327538AJul 5, 1994
Method of utilizing common buses in a multiprocessor system
CANON KK29 citations92
US5737568AApr 7, 1998
Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory
CANON KK19 citations83
US6021472AFeb 1, 2000
Information processing device and control method thereof
CANON KK7 citations74
US5995751ANov 30, 1999
Information processing apparatus
CANON KK13 citations73
US5933261AAug 3, 1999
Information processing method and system
CANON KK13 citations73
US5577218ANov 19, 1996
Memory access control method wherein block access is performed as a sequential access to an address updated by incrementation
CANON KK6 citations62