Inventor
SCHWARZ ERIC MARK
US26 patents
Patents
26 patentsUS6009261ADec 28, 1999
Preprocessing of stored target routines for emulating incompatible instructions on a target processor
IBM536 citations97
US6075937AJun 13, 2000
Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation
IBM78 citations94
US5764555AJun 9, 1998
Method and system of rounding for division or square root: eliminating remainder calculation
IBM135 citations93
US7493480B2Feb 17, 2009
Method and apparatus for prefetching branch history information
IBM45 citations92
US6049860AApr 11, 2000
Pipelined floating point stores
IBM26 citations92
US5903479AMay 11, 1999
Method and system for executing denormalized numbers
IBM22 citations92
US5737255AApr 7, 1998
Method and system of rounding for quadratically converging division or square root
IBM24 citations92
US5729481AMar 17, 1998
Method and system of rounding for quadratically converging division or square root
IBM18 citations92
US6044454AMar 28, 2000
IEEE compliant floating point unit
IBM39 citations90
US5687106ANov 11, 1997
Implementation of binary floating point using hexadecimal floating point unit
IBM37 citations89
US6055554AApr 25, 2000
Floating point binary quad word format multiply instruction unit
IBM9 citations74
US6105126AAug 15, 2000
Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code
IBM12 citations73
US6085313AJul 4, 2000
Computer processor system for executing RXE format floating point instructions
IBM13 citations73
US11360769B1Jun 14, 2022
Decimal scale and convert and split to hexadecimal floating point instruction
IBM5 citations72
US5757682AMay 26, 1998
Parallel calculation of exponent and sticky bit during normalization
IBM7 citations72
US5742535AApr 21, 1998
Parallel calculation of exponent and sticky bit during normalization
IBM5 citations72
US10903988B1Jan 26, 2021
Unique instruction identifier that identifies common instructions across different code releases
IBM5 citations65
US6021422AFeb 1, 2000
Partitioning of binary quad word format multiply instruction on S/390 processor
IBM7 citations63
US12223290B2Feb 11, 2025
Decimal floating-point instruction in a round-for-reround mode
IBM0 citations62
US11698772B2Jul 11, 2023
Prepare for shorter precision (round for reround) mode in a decimal floating-point instruction
IBM0 citations62
US11663004B2May 30, 2023
Vector convert hexadecimal floating point to scaled decimal instruction
IBM1 citations62
US11442726B1Sep 13, 2022
Vector pack and unpack instructions
IBM1 citations62
US11327766B2May 10, 2022
Instruction dispatch routing
IBM0 citations61
US5742536AApr 21, 1998
Parallel calculation of exponent and sticky bit during normalization
IBM2 citations61
US5654911AAug 5, 1997
Carry select and input select adder for late arriving data
IBM3 citations61
US11531546B2Dec 20, 2022
Hexadecimal floating point multiply and add instruction
IBM0 citations51