Inventor
WANN HSING-JEN C
US8 patents
Patents
8 patentsUS6268640B1Jul 31, 2001
Forming steep lateral doping distribution at source/drain junctions
IBM171 citations98
US7056794B2Jun 6, 2006
FET gate structure with metal gate electrode and silicide contact
IBM96 citations96
US6025242AFeb 15, 2000
Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
IBM22 citations92
US5998248ADec 7, 1999
Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
IBM19 citations92
US5998273ADec 7, 1999
Fabrication of semiconductor device having shallow junctions
IBM25 citations92
US6022771AFeb 8, 2000
Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
IBM14 citations73
US6974736B2Dec 13, 2005
Method of forming FET silicide gate structures incorporating inner spacers
IBM10 citations72
US6975133B1Dec 13, 2005
Logic circuits having linear and cellular gate transistors
IBM0 citations47