Inventor

ALESHIN STANISLAV V

SU42 patents

⚠️ This page may combine multiple inventors who share the name “ALESHIN STANISLAV V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALESHIN STANISLAV V

LSI LOGIC CORP

Hexagonal architecture

Architecture having diamond shaped or parallelogram shaped cells

CAD for hexagonal architecture

Hexagonal field programmable gate array architecture

Hexagonal DRAM array

Microelectronic integrated circuit including triangular CMOS &#34;nand&#34; gate device

Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints

Tri-directional interconnect architecture for SRAM

Transistors having dynamically adjustable characteristics

Hexagonal sense cell architecture

Mask having an arbitrary complex transmission function

Polydirectional non-orthoginal three layer interconnect architecture

Hexagonal architecture with triangular shaped cells

Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints

Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters

Geometric aerial image simulation

Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization

Triangular semiconductor or gate

Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip

Programmable triangular shaped device having variable gain

Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple &#34;jiggles&#34;

Triangular semiconductor NAND gate

Physical design automation system and method using monotonically improving linear clusterization

Method and system for constructing a hierarchy-driven chip covering for optical proximity correction

Gradient method of mask edge correction

Mask correction for photolithographic processes

Triangular semiconductor &#34;AND&#34; gate device

Hexagonal SRAM architecture

Microelectronic integrated circuit including triangular semiconductor &#34;or&#34;g

Optical proximity correction driven hierarchy

Method and system for analyzing the quality of an OPC mask

Microelectronic integrated circuit including triangular semiconductor &#34;and&#34; gate device

Resynthesis method for significant delay reduction

Quality measurement of an aerial image

Physical design automation system and process for designing integrated circuit chips using generalized assignment

Automatic recognition of an optically periodic structure in an integrated circuit design

Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes

LSI CORP

OPC edge correction based on a smoothed mask design

Method and system for improving aerial image simulation speeds

Automatic recognition of geometric points in a target IC design for OPC mask quality calculation

Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes

LIS LOGIC CORP

Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry

Microelectronic integrated circuit including triangular CMOS "nand" gate device

Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles"

Triangular semiconductor "AND" gate device

Microelectronic integrated circuit including triangular semiconductor "or"g

Microelectronic integrated circuit including triangular semiconductor "and" gate device