Inventor

HSU CHEN-CHUNG

TW98 patents

⚠️ This page may combine multiple inventors who share the name “HSU CHEN-CHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU CHEN-CHUNG

UNITED MICROELECTRONICS CORP

Method of making ROM components

ROM device having memory units arranged in three dimensions, and a method of making the same

Trench method for three dimensional chip connecting during IC fabrication

Three-dimensional multichip package

Three-dimensional multichip package and methods of fabricating

Dual damascene manufacturing process

Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method

Process for fabricating a recessed gate MOS device

Method of making a flash memory cell having an asymmetric source and drain pocket structure

Method for fabricating read-only memory device with a three-dimensional memory cell structure

Method of making silicided LDD with recess in semiconductor substrate

Method for fabricating MOS device with reduced anti-punchthrough region

Method of manufacturing borderless contact

Electrostatic discharge device

Method of manufacturing self-aligned contact

Electrostatic discharge protection circuit

Field device electrostatic discharge protective circuit

Method of fabricating a dual damascene structure

Damascene manufacturing process capable of forming borderless via

Structure of manufacturing an electrostatic discharge protective circuit for SRAM

Self-aligned silicide (salicide) process for electrostatic discharge (ESD) protection

Stacked and trench type DRAM capacitor

Structure and manufacturing method for DRAM capacitors

Electromigration test pattern simulating semiconductor components

Process for fabricating read-only memory cells using removable barrier strips

Multichip module having a multi-level configuration

Process for fabricating read-only memory cells

Vertical channel device having buried source

VLSI ROM programmed by selective diode formation

Trench isolation method for CMOS transistor

Process for fabricating a semiconductor electrostatic discharge (ESD) protective device

Field edge manufacture of a T-gate LDD pocket device

Ion implanted programmable cell for read only memory applications

Method of elimination of junction punchthrough leakage via buried sidewall isolation

Method of making a shallow trench large-angle-tilt implanted drain device

Method for manufacturing electrostatic discharge devices

Metal-oxide-semiconductor field-effect transistor and its method of fabrication

Method of making high density ROM, without using a code implant

Method of fabricating lightly doped drain transistor device

Thin film delamination test chip

Method of making a vertical channel device using buried source techniques

Lightly doped drain transistor device having the polysilicon sidewall spacers

Concave channel MOS transistor and method of fabricating the same

Method of fabricating semiconductor device for preventing antenna effect

Method of manufacturing electrostatic discharge protective circuit

Method and apparatus for testing the reliability of semiconductor terminals

Method of fabricating a dual damascene structure

Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit

UNITED MICROELECTRONICWS CORP

Recessed lightly doped drain (LDD) for higher performance MOSFET

UNITED MICROELETRONICS CORP

Method of manufacturing a buried contact in a static random access memory