Inventor

PARKS TERRY

US237 patents

⚠️ This page may combine multiple inventors who share the name “PARKS TERRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARKS TERRY

IP FIRST LLC

Static branch prediction mechanism for conditional branch instructions

Selective interrupt suppression

Apparatus for performing branch target address calculation based on branch type

Hybrid branch predictor with improved selector table update mechanism

Microprocessor apparatus and method for performing block cipher cryptographic functions

Apparatus and method for extending a microprocessor instruction set

Mechanism for extending the number of registers in a microprocessor

Microprocessor apparatus and method for performing block cipher cryptographic functions

Apparatus and method for selective memory attribute control

Apparatus and method for extending a microprocessor instruction set

Random number generator with selectable dual random bit string engines

Random number generator bit string filter

Pop-compare micro instruction for repeat string operations

Continuous multi-buffering random number generator

Method and apparatus for performing branch prediction combining static and dynamic branch predictors

Apparatus and method for fast forward branch

Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file

Method and apparatus for improved aligned/misaligned data load from cache

Apparatus and method for performing transparent block cipher cryptographic functions

Apparatus and method for target address replacement in speculative branch target address cache

Method and apparatus for speculative microinstruction pairing

VIA TECH INC

Initialization of a microprocessor providing for execution of secure code

Processor that performs approximate computing instructions

Apparatus and method for secure hash algorithm

Microprocessor apparatus providing for secure interrupts and exceptions

Apparatus and method for instruction-level specification of floating point format

Microprocessor apparatus and method for providing configurable cryptographic block cipher round results

Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor

Apparatus and method for generating a cryptographic key schedule in a microprocessor

HENRY G GLENN

Apparatus and method for managing a microprocessor providing for a secure execution mode

Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

Termination of secure execution mode in a microprocessor providing for execution of secure code

Microprocessor having secure non-volatile storage access

VIA ALLIANCE SEMICONDUCTOR CO LTD

Neural network unit with shared activation function units

Multi-operation neural network unit

Neural network unit that performs stochastic rounding

Neural network unit that performs convolutions using collective shift register among array of neural processing units

INTEGRATED DEVICE TECH

Apparatus and method for exception handling during micro code string instructions

Apparatus and method for of register changes during execution of a micro instruction tracking sequence

Method and apparatus for selector storing and restoration

Apparatus and method for processing exceptions during execution of string instructions

DELL USA LP

PDA having chord keyboard input device and method of providing data thereto

Method and apparatus for low latency synchronization of signals having different clock speeds

DELLUSA L P

Ternary storage dynamic RAM

LONGVIEW FIBRE CO

Paperboard container for liquids including an improved structure to prevent fitment rotation

PARKS TERRY

Microprocessor that fuses MOV/ALU instructions

CRISPIN THOMAS A

Atomic hash instruction

COL GERARD M

Microprocessor with fused store address/store data microinstruction

I P FIRST LLC

Paired register exchange using renaming register map

I P FIRST L L C

Method and apparatus for predicting conditional branch instruction outcome based on branch condition test type