Inventor

PLAT MARINA V

US59 patents

⚠️ This page may combine multiple inventors who share the name “PLAT MARINA V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PLAT MARINA V

ADVANCED MICRO DEVICES INC

Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning

Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines

Bi-layer trim etch process to form integrated circuit gate structures

Use of silicon containing imaging layer to define sub-resolution gate structures

RELACS process to double the frequency or pitch of small feature formation

Damascene process for a T-shaped gate electrode

Antireflective bi-layer hardmask including a densified amorphous carbon layer

CVD organic polymer film for advanced gate patterning

Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices

Dual inlaid process using a bilayer resist

Multilayer anti-reflective coating process for integrated circuit fabrication

Bright field image reversal for contact hole patterning

Use of silicon oxynitride ARC for metal layers

Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer

Minimization of line width variation in photolithography

Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

Silicon barrier layer to prevent resist poisoning

Method of making a memory cell with polished insulator layer

Two mask photoresist exposure pattern for dense and isolated regions

Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer

System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process

Method of strengthening photoresist to prevent pattern collapse

Semiconductor manufacturing method using a dielectric photomask

Multilayer low reflectivity hard mask and process therefor

Methods for designing grating structures for use in situ scatterometry to detect photoresist defects

Negative resist or dry develop process for forming middle of line implant layer

Enhanced transistor gate using E-beam radiation

Two mask photoresist exposure pattern for dense and isolated regions

Patterning with rigid organic under-layer

Method for patterning a feature using a trimmed hardmask

Method for semiconductor gate line dimension reduction

Method for reducing gate line deformation and reducing gate line widths in semiconductor devices

Method of enhancing gate patterning properties with reflective hard mask

Dual damascene process utilizing a bi-layer imaging layer

Multilayer anti-reflective coating for semiconductor lithography

Process for etching an organic dielectric using a silyated photoresist mask

Connection structures for integrated circuits and processes for their formation

Measuring BARC thickness using scatterometry

Etch bias distribution across semiconductor wafer

Dual inlaid process using an imaging layer to protect via from poisoning

Dark field image reversal for gate or line patterning

Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer

Method and system for reducing ARC layer removal by condensing the ARC layer

Resist developing method and apparatus with nozzle offset for uniform developer application

Patterning for elliptical Vss contact on flash memory

Dual bake for BARC fill without voids

Method for semiconductor gate line dimension reduction

E-beam flood exposure of spin-on material to eliminate voids in vias

(unassigned)

Etch bias distribution across semiconductor wafer

CLARIANT FINANCE BVI LTD

Method of developing positive photoresist and compositions therefor